公开(公告)号：WO1996017292A1

公开(公告)日：1996-06-06

申请号：PCT/US1995015719

申请日：1995-12-01

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  PELEG, Alexander ,  YAARI, Yaakov ,  MITTAL, Millind ,  MENNEMEIER, Larry, M. ,  EITAN, Benny

IPC: G06F07/20

CPC classification number: G06F9/30014 ,  G06F7/026 ,  G06F9/30021 ,  G06F9/30036 ,  G06F2207/3828

Abstract: A processor includes a decoder (202) coupled to receive a control signal (207). The control signal has a first source address (602), a second source address (603), a destination address (605), and an operation field (601). The first source address corresponds to a first location, and the second source address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data compare operation is to be performed. The processor includes a circuit coupled to the decoder for comparing a first packed data being stored at the first location with a second packed data being stored at the second location and for communicating a corresponding result packed data to the third location.

Abstract translation: 处理器包括耦合以接收控制信号（207）的解码器（202）。 控制信号具有第一源地址（602），第二源地址（603），目的地地址（605）和操作区（601）。 第一源地址对应于第一位置，第二源地址对应于第二位置。 目的地址对应于第三个位置。 操作字段指示要执行打包数据比较操作的类型。 处理器包括耦合到解码器的电路，用于将在第一位置处存储的第一打包数据与存储在第二位置处的第二打包数据进行比较，并将相应的结果打包数据传送到第三位置。

公开(公告)号：WO1996017291A1

公开(公告)日：1996-06-06

申请号：PCT/US1995015713

申请日：1995-12-01

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  PELEG, Alexander ,  YAARI, Yaakov ,  MITTAL, Millind ,  MENNEMEIER, Larry, M. ,  EITAN, Benny

IPC: G06F07/14

CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

Abstract: A processor includes a first register (209) for storing a first packed data, a decoder (202), and a functional unit (203). The decoder has a control signal input (207) for receiving a first control signal and a second control signal. The first control signal is for indicating a pack operation, and the second control signal is for indicating an unpack operation. The functional unit is coupled to the decoder (202) and the register (209). The functional unit performs the pack operation and the unpack operation using the first packed data as well as move operation.

Abstract translation: 处理器包括用于存储第一打包数据的第一寄存器（209），解码器（202）和功能单元（203）。 解码器具有用于接收第一控制信号和第二控制信号的控制信号输入（207）。 第一控制信号用于指示包操作，第二控制信号用于指示解包操作。 功能单元耦合到解码器（202）和寄存器（209）。 功能单元使用第一打包数据以及移动操作来执行包操作和解包操作。

公开(公告)号：WO1996017293A1

公开(公告)日：1996-06-06

申请号：PCT/US1995015681

申请日：1995-12-01

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  PELEG, Alexander ,  YAARI, Yaakov ,  MITTAL, Millind ,  MENNEMEIER, Larry, M. ,  EITAN, Benny

IPC: G06F07/52

CPC classification number: G06F7/53 ,  G06F7/49921 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/3885 ,  G06F2207/3828

Abstract: A processor (109) includes a decoder (202) being coupled to receive a control signal (207). The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data multiply operation is to be performed. The processor further includes a circuit (203) being coupled to the decoder. The circuit is for multiplying a first packed data being stored at the first location with a second packed data being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.

Abstract translation: 处理器（109）包括被耦合以接收控制信号（207）的解码器（202）。 控制信号具有第一源地址，第二源地址，目的地地址和操作字段。 第一个源地址对应于第一个位置。 第二地址对应于第二位置。 目的地址对应于第三个位置。 操作字段指示要执行一种打包数据乘法运算。 处理器还包括耦合到解码器的电路（203）。 该电路用于将在第一位置处存储的第一打包数据与存储在第二位置处的第二打包数据相乘。 电路还用于将相应的结果打包数据传送到第三位置。

公开(公告)号：WO1996017289A1

公开(公告)日：1996-06-06

申请号：PCT/US1995015682

申请日：1995-12-01

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  PELEG, Alexander ,  YAARI, Yaakov ,  MITTAL, Millind ,  MENNEMEIER, Larry, M. ,  EITAN, Benny

IPC: G06F05/01

CPC classification number: G06F7/76 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30167

Abstract: The processor (109) includes a decoder (202) being coupled to receive a control signal (207). The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second source address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data shift operation is to be performed. The processor further includes a circuit (203) being coupled to the decoder. The circuit is for shifting a first packed data being stored at the first location by a value being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.

Abstract translation: 处理器（109）包括被耦合以接收控制信号（207）的解码器（202）。 控制信号具有第一源地址，第二源地址，目的地地址和操作字段。 第一个源地址对应于第一个位置。 第二源地址对应于第二位置。 目的地址对应于第三个位置。 操作字段指示将执行一种打包数据移位操作。 处理器还包括耦合到解码器的电路（203）。 电路用于将存储在第一位置的第一打包数据移位存储在第二位置的值。 电路还用于将相应的结果打包数据传送到第三位置。

公开(公告)号：EP0795154A1

公开(公告)日：1997-09-17

申请号：EP95943654.0

申请日：1995-12-01

Applicant: INTEL CORPORATION

Inventor： PELEG, Alexander ,  YAARI, Yaakov ,  MITTAL, Millind ,  MENNEMEIER, Larry, M. ,  EITAN, Benny

IPC: G06F7 ,  G06F9

CPC classification number: G06F9/30014 ,  G06F7/026 ,  G06F9/30021 ,  G06F9/30036 ,  G06F2207/3828

Abstract: A processor includes a decoder (202) coupled to receive a control signal (207). The control signal has a first source address (602), a second source address (603), a destination address (605), and an operation field (601). The first source address corresponds to a first location, and the second source address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data compare operation is to be performed. The processor includes a circuit coupled to the decoder for comparing a first packed data being stored at the first location with a second packed data being stored at the second location and for communicating a corresponding result packed data to the third location.

公开(公告)号：EP0795155B1

公开(公告)日：2003-03-19

申请号：EP95944602.2

申请日：1995-12-01

Applicant: INTEL CORPORATION

Inventor： PELEG, Alexander ,  YAARI, Yaakov ,  MITTAL, Millind ,  MENNEMEIER, Larry, M. ,  EITAN, Benny

IPC: G06F7/52 ,  G06F9/30

CPC classification number: G06F7/53 ,  G06F7/49921 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/3885 ,  G06F2207/3828

公开(公告)号：EP0795155A1

公开(公告)日：1997-09-17

申请号：EP95944602.0

申请日：1995-12-01

Applicant: INTEL CORPORATION

Inventor： PELEG, Alexander ,  YAARI, Yaakov ,  MITTAL, Millind ,  MENNEMEIER, Larry, M. ,  EITAN, Benny

IPC: G06F9 ,  G06F5 ,  G06F7

CPC classification number: G06F7/53 ,  G06F7/49921 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/3885 ,  G06F2207/3828

Abstract: A processor (109) includes a decoder (202) being coupled to receive a control signal (207). The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data multiply operation is to be performed. The processor further includes a circuit (203) being coupled to the decoder. The circuit is for multiplying a first packed data being stored at the first location with a second packed data being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.

Abstract translation: 处理器（109）包括被耦合以接收控制信号（207）的解码器（202）。 控制信号具有第一源地址，第二源地址，目的地地址和操作字段。 第一个源地址对应于第一个位置。 第二个地址对应于第二个地址。 目的地地址对应于第三地点。 操作字段表示将执行一种打包数据乘法操作。 处理器还包括耦合到解码器的电路（203）。 该电路用于将存储在第一位置的第一打包数据与存储在第二位置的第二打包数据相乘。 该电路还用于将对应的结果打包数据传送到第三位置。

公开(公告)号：EP0795153A1

公开(公告)日：1997-09-17

申请号：EP95943362.0

申请日：1995-12-01

Applicant: INTEL CORPORATION

Inventor： PELEG, Alexander ,  YAARI, Yaakov ,  MITTAL, Millind ,  MENNEMEIER, Larry, M. ,  EITAN, Benny

IPC: G06F9

CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

Abstract: A processor includes a first register (209) for storing a first packed data, a decoder (202), and a functional unit (203). The decoder has a control signal input (207) for receiving a first control signal and a second control signal. The first control signal is for indicating a pack operation, and the second control signal is for indicating an unpack operation. The functional unit is coupled to the decoder (202) and the register (209). The functional unit performs the pack operation and the unpack operation using the first packed data as well as move operation.

Abstract translation: 处理器包括用于存储第一打包数据的第一寄存器（209），解码器（202）和功能单元（203）。 解码器具有用于接收第一控制信号和第二控制信号的控制信号输入（207）。 第一控制信号用于指示包操作，第二控制信号用于指示解包操作。 功能单元耦合到解码器（202）和寄存器（209）。 功能单元使用第一打包数据以及移动操作来执行包操作和解包操作。