公开(公告)号：EP1493098A4

公开(公告)日：2009-11-11

申请号：EP03736460

申请日：2003-04-10

Applicant: INTERDIGITAL TECH CORP

Inventor： BUCHERT RYAN SAMUEL ,  SHAHRIER SHARIF M ,  BECKER PETER

IPC: G06F17/14

CPC classification number: G06F17/144

Abstract: An apparatus and method for DFT processing using prime factor algorithm (PFA) on a selected number P of midamble chip values received by a CDMA receiver, where P has a plurality M of relatively prime factors F, and the DFT process is divided into M successive F-point DFT processes. The P data values are retrieved from a single input port memory and selectively permuted by a controller into parallel caches to optimize factoring with associated twiddle factors stored in parallel registers. The permuted inputs are factored in two or more parallel PFA circuits that comprise adders and multipliers arranged to accommodate any size F-point DFT. The outputs of the PFA circuits are processed by consolidation circuitry in preparation for output permutation of the values which are sent to memory for subsequent DFT cycles.

公开(公告)号：HK1074269A1

公开(公告)日：2005-11-04

申请号：HK05108196

申请日：2005-09-20

Applicant: INTERDIGITAL TECH CORP

Inventor： BUCHERT RYAN SAMUEL ,  SHAHRIER SHARIF M ,  BECKER PETER

IPC: G06F20060101 ,  G06F17/14

Abstract: An apparatus and method for DFT processing using prime factor algorithm (PFA) on a selected number P of midamble chip values received by a CDMA receiver, where P has a plurality M of relatively prime factors F, and the DFT process is divided into M successive F-point DFT processes. The P data values are retrieved from a single input port memory and selectively permuted by a controller into parallel caches to optimize factoring with associated twiddle factors stored in parallel registers. The permuted inputs are factored in two or more parallel PFA circuits that comprise adders and multipliers arranged to accommodate any size F-point DFT. The outputs of the PFA circuits are processed by consolidation circuitry in preparation for output permutation of the values which are sent to memory for subsequent DFT cycles.

公开(公告)号：AU2003237804A1

公开(公告)日：2003-12-19

申请号：AU2003237804

申请日：2003-04-10

Applicant: INTERDIGITAL TECH CORP

Inventor： BUCHERT RYAN SAMUEL ,  SHAHRIER SHARIF M ,  BECKER PETER

IPC: G06F17/14

Abstract: An apparatus and method for DFT processing using prime factor algorithm (PFA) on a selected number P of midamble chip values received by a CDMA receiver, where P has a plurality M of relatively prime factors F, and the DFT process is divided into M successive F-point DFT processes. The P data values are retrieved from a single input port memory and selectively permuted by a controller into parallel caches to optimize factoring with associated twiddle factors stored in parallel registers. The permuted inputs are factored in two or more parallel PFA circuits that comprise adders and multipliers arranged to accommodate any size F-point DFT. The outputs of the PFA circuits are processed by consolidation circuitry in preparation for output permutation of the values which are sent to memory for subsequent DFT cycles.

公开(公告)号：AT403288T

公开(公告)日：2008-08-15

申请号：AT04716100

申请日：2004-03-01

Applicant: INTERDIGITAL TECH CORP

Inventor： SUPPLEE STEPHAN ,  TIMMERMAN CHAYIL ,  BUCHERT RYAN ,  BECKER PETER ,  NASUTI TONINO ,  DIFAZIO ROBERT ,  HAIM JOHN

IPC: H04B7/216 ,  H04B1/707

Abstract: Multi-user detection (MUD) performance is optimized to eliminate redundant use of power during processing. An overbuilt A-matrix, i.e., a system response matrix, is provided. The overbuilt A-matrix uses all possible codes, e.g., all codes identified in a candidate code list (CCL) provided by blind code detection (BCD). The overbuilt A-matrix is passed to the MUD which extracts only those rows or columns required for codes that have actually been received, thus eliminating the need to recompute whitening matched filter (WMF) outputs that do not correspond to the actually received code.