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    OPTIMIZED DISCRETE FOURIER TRANSFORM METHOD AND APPARATUS USING PRIME FACTOR ALGORITHM
    2.
    发明公开
    OPTIMIZED DISCRETE FOURIER TRANSFORM METHOD AND APPARATUS USING PRIME FACTOR ALGORITHM 审中-公开
    方法和设备改进的离散傅立叶变换到PRIMFAKTORALGORITHMUS

    公开(公告)号：EP1493098A4

    公开(公告)日：2009-11-11

    申请号：EP03736460

    申请日：2003-04-10

    Applicant: INTERDIGITAL TECH CORP

    Inventor： BUCHERT RYAN SAMUEL ,  SHAHRIER SHARIF M ,  BECKER PETER

    IPC: G06F17/14

    CPC classification number: G06F17/144

    Abstract: An apparatus and method for DFT processing using prime factor algorithm (PFA) on a selected number P of midamble chip values received by a CDMA receiver, where P has a plurality M of relatively prime factors F, and the DFT process is divided into M successive F-point DFT processes. The P data values are retrieved from a single input port memory and selectively permuted by a controller into parallel caches to optimize factoring with associated twiddle factors stored in parallel registers. The permuted inputs are factored in two or more parallel PFA circuits that comprise adders and multipliers arranged to accommodate any size F-point DFT. The outputs of the PFA circuits are processed by consolidation circuitry in preparation for output permutation of the values which are sent to memory for subsequent DFT cycles.

    CDMA SYSTEM TRANSMISSION MATRIX COEFFICIENT CALCULATION
    5.
    发明公开
    CDMA SYSTEM TRANSMISSION MATRIX COEFFICIENT CALCULATION 有权
    BERECHNUNG VON公司

    公开(公告)号：EP1529358A4

    公开(公告)日：2005-09-14

    申请号：EP03742132

    申请日：2003-06-23

    Applicant: INTERDIGITAL TECH CORP

    Inventor： TIMMERMAN CHAYIL S ,  BUCHERT RYAN SAMUEL

    IPC: H04B1/707 ,  H04B7/155 ,  H04B7/212 ,  H04B7/216 ,  H04L25/02 ,  H04Q7/38

    CPC classification number: H04B1/7105 ,  H04B2201/70707 ,  H04L25/0212

    Abstract: A hermetian of a system response matrix is to be determined. Spreading codes, channel specific multipliers and channel impulse responses are provided. The channel code specific multipliers have real and imaginary values. Channel codes being a combination of a real spreading code, a complex scrambling code and a sign of the channel code specific multiplier. Real and imaginary components (JAD and AC) of an approximate hermetian of the system response matrix are determined. The channel code specific multipliers are applied to the real and imaginary components (JAD and AC) of a result of the convolutions to derive the hermetian of the system response matrix.

    Abstract translation: 系统响应矩阵的hermetian将被确定。 提供扩频码，信道特定乘法器和信道脉冲响应。 通道代码特定的乘法器具有实数和虚数值。 信道码是实际扩频码，复数扰码和信道码特定乘数的符号的组合。 确定系统响应矩阵的近似Hermetian的实部和虚部（JAD和AC）。 信道代码特定的乘法器被应用于卷积结果的实部和虚部（JAD和AC）以导出系统响应矩阵的幂次。

    INSERTION SORTER
    6.
    发明公开
    INSERTION SORTER 有权
    EINFÜGE-SORTIERER

    公开(公告)号：EP1459466A4

    公开(公告)日：2005-01-26

    申请号：EP02806169

    申请日：2002-12-18

    Applicant: INTERDIGITAL TECH CORP

    Inventor： BUCHERT RYAN SAMUEL ,  TIMMERMAN CHAYIL ,  KIM YOUNGLOK

    IPC: G06F7/24 ,  H04J3/04 ,  H04J3/00

    CPC classification number: G06F7/24 ,  H04J3/047

    Abstract: An insertion sorter circuit (200) and method are provided which are particularly useful for sorting channel response values of a communication signal. The sorter circuit includes a series of sorter elements (1501-150N) which each have a register (1011-101N). The circuit is configured to cascade values downwardly when one register receives a greater value than it has stored (1021-102N), which value is not greater than the value stored in any upstream register. At the end of processing the values, the most significant values are stored in the registers (1011-101N), the sum (105) of which are the channel power estimate. The channel noise (106) variance is obtainable by applying a system dependent scaling factor to the sum (105) of the least significant values processed.

    Abstract translation: 提供了一种插入分拣机电路和方法，其特别用于对通信信号的通道响应值进行排序。 分拣机电路包括一系列各自具有寄存器的分拣机元件。 该电路被配置为当一个寄存器接收到比它存储的值更大的值时向下级联值，该值不大于存储在任何上游寄存器中的值。 在处理这些值的最后，最重要的值存储在寄存器中，其总和是信道功率估计。 通过将系统相关的缩放因子应用于所处理的最低有效值的和来获得信道噪声方差。

    7.
    发明专利
    未知

    公开(公告)号：DE602004015426D1

    公开(公告)日：2008-09-11

    申请号：DE602004015426

    申请日：2004-03-01

    Applicant: INTERDIGITAL TECH CORP

    Inventor： SUPPLEE STEPHAN SHANE ,  TIMMERMAN CHAYIL S ,  BUCHERT RYAN SAMUEL ,  BECKER PETER EDWARD ,  NASUTI TONINO ,  DIFAZIO ROBERT A ,  HAIM JOHN W

    IPC: H04B7/216 ,  H04B1/707

    Abstract: Multi-user detection (MUD) performance is optimized to eliminate redundant use of power during processing. An overbuilt A-matrix, i.e., a system response matrix, is provided. The overbuilt A-matrix uses all possible codes, e.g., all codes identified in a candidate code list (CCL) provided by blind code detection (BCD). The overbuilt A-matrix is passed to the MUD which extracts only those rows or columns required for codes that have actually been received, thus eliminating the need to recompute whitening matched filter (WMF) outputs that do not correspond to the actually received code.

    Optimized discrete fourier transform method and apparatus using prime factor algorithm
    8.
    发明专利
    Optimized discrete fourier transform method and apparatus using prime factor algorithm 未知

    公开(公告)号：HK1074269A1

    公开(公告)日：2005-11-04

    申请号：HK05108196

    申请日：2005-09-20

    Applicant: INTERDIGITAL TECH CORP

    Inventor： BUCHERT RYAN SAMUEL ,  SHAHRIER SHARIF M ,  BECKER PETER

    IPC: G06F20060101 ,  G06F17/14

    Abstract: An apparatus and method for DFT processing using prime factor algorithm (PFA) on a selected number P of midamble chip values received by a CDMA receiver, where P has a plurality M of relatively prime factors F, and the DFT process is divided into M successive F-point DFT processes. The P data values are retrieved from a single input port memory and selectively permuted by a controller into parallel caches to optimize factoring with associated twiddle factors stored in parallel registers. The permuted inputs are factored in two or more parallel PFA circuits that comprise adders and multipliers arranged to accommodate any size F-point DFT. The outputs of the PFA circuits are processed by consolidation circuitry in preparation for output permutation of the values which are sent to memory for subsequent DFT cycles.

    9.
    发明专利
    未知

    公开(公告)号：NO20051806L

    公开(公告)日：2005-06-08

    申请号：NO20051806

    申请日：2005-04-13

    Applicant: INTERDIGITAL TECH CORP

    Inventor： SUPPLEE STEPHAN SHANE ,  BUCHERT RYAN SAMUEL ,  TIMMERMAN CHAYIL

    IPC: G06F5/01 ,  G06F7/00 ,  G06F7/38 ,  G06F7/52 ,  G06F17/16 ,  G06K20060101

    Abstract: A method and system for performing many different types if algorithms utilizes a single mathematical engine (30) such that the mathematical engine is capable of utilizing the same multipliers for all of the algorithms. The mathematical engine includes a selectively controlled parallel output register (33), at least one selectively controlled memory (31), and a plurality of processing elements (40). The output register, the memory and the processing elements are selectively controlled depending upon the algorithm to be performed.

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