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    MODULAR BASE STATION WITH VARIABLE COMMUNICATION CAPACITY
    1.
    发明申请
    MODULAR BASE STATION WITH VARIABLE COMMUNICATION CAPACITY 审中-公开
    具有可变通信能力的模块化基站

    公开(公告)号：WO9948228A9

    公开(公告)日：2000-07-27

    申请号：PCT/US9905776

    申请日：1999-03-17

    Applicant: INTERDIGITAL TECH CORP ,  POLAN JEFFREY ,  DICK STEPHEN G ,  KAZAKEVICH LEONID ,  OZLUTURK FATIH M ,  REGIS ROBERT T ,  TURNER RICHARD

    Inventor： POLAN JEFFREY ,  DICK STEPHEN G ,  KAZAKEVICH LEONID ,  OZLUTURK FATIH M ,  REGIS ROBERT T ,  TURNER RICHARD

    IPC: H04B7/26 ,  H04W88/08 ,  H04Q7/36

    CPC classification number: H04W88/08 ,  H04B7/2628 ,  Y02D70/00 ,  Y02D70/1222 ,  Y02D70/449

    Abstract: The present invention provides a base station architecture that is modular in configuration, lowering the initial cost of implementing a new CDMA telecommunication system for a defined geographical region while allowing for future capacity. The scalable architecture is assembled from a digital base station unit that is configured to support a plurality of simultaneous wireless calls connecting to a conventional public switched telephone network. For initial startup, two base station units are deployed for redundancy in case of a single failure. Additional base station units may be added when the need arises for extra traffic capacity. If sectorization is required, the base station units may be directionally oriented. Coupled to and remote from each base station unit are two amplified antenna modules that contain an omni-directional or an external directional antenna, a high power RF amplifier for transmitted frequencies and a low noise amplifier for received frequencies. A separate power supply module capable of supporting two base station units provides continued service in the event of a mains power outage.

    Abstract translation: 本发明提供了一种模块化配置的基站架构，降低了为所定义的地理区域实施新的CDMA电信系统的初始成本，同时允许将来的容量。 可扩展架构由数字基站单元组合，数字基站单元被配置为支持连接到常规公共交换电话网络的多个同时无线呼叫。 对于初始启动，在单个故障的情况下，部署了两个基站单元以实现冗余。 当需要额外的流量时，可以添加额外的基站单元。 如果需要扇区化，则基站单元可以是定向的。 耦合到每个基站单元并且远离每个基站单元的两个放大天线模块包含全向或外部定向天线，用于发射频率的高功率RF放大器和用于接收频率的低噪声放大器。 能够支持两个基站单元的单独的电源模块在主电源中断的情况下提供持续的服务。

    6.
    发明专利
    未知

    公开(公告)号：AT216100T

    公开(公告)日：2002-04-15

    申请号：AT97933270

    申请日：1997-06-27

    Applicant: INTERDIGITAL TECH CORP

    Inventor： REGIS ROBERT T

    IPC: G06F13/376 ,  G06F13/374 ,  H04B1/7075 ,  H04B1/708

    Abstract: A parallel packetized intermodule arbitrated high speed control data bus system which allows high speed communications between microprocessor modules in a more complex digital processing environment. The system features a simplified hardware architecture featuring fast FIFO queuing operating at 12.5 MHz, TTL CMOS compatible level clocking signals, single bus master arbitration, synchronous clocking, DMA, and unique module addressing for multiprocessor systems. The system includes a parallel data bus with sharing bus masters residing on each processing module decreeing the communication and data transfer protocols. Bus arbitration is performed over a dedicated serial arbitration line and each requesting module competes for access to the parallel data bus by placing the address of the requesting module on the arbitration line and monitoring the arbitration line for collisions.

    7.
    发明专利
    未知

    公开(公告)号：AT212488T

    公开(公告)日：2002-02-15

    申请号：AT99914923

    申请日：1999-03-17

    Applicant: INTERDIGITAL TECH CORP

    Inventor： POLAN JEFFREY ,  DICK STEPHEN G ,  KAZAKEVICH LEONID ,  OZLUTURK FATIH M ,  REGIS ROBERT T ,  TURNER RICHARD

    IPC: H04B7/26 ,  H04W88/08 ,  H04Q7/36

    Abstract: The present invention provides a base station architecture that is modular in configuration, lowering the initial cost of implementing a new CDMA telecommunication system for a defined geographical region while allowing for future capacity. The scalable architecture is assembled from a digital base station unit that is configured to support a plurality of simultaneous wireless calls connecting to a conventional public switched telephone network. For initial startup, two base station units are deployed for redundancy in case of a single failure. Additional base station units may be added when the need arises for extra traffic capacity. If sectorization is required, the base station units may be directionally oriented. Coupled to and remote from each base station unit are two amplified antenna modules that contain an omni-directional or an external directional antenna, a high power RF amplifier for transmitted frequencies and a low noise amplifier for received frequencies. A separate power supply module capable of supporting two base station units provides continued service in the event of a mains power outage.

    8.
    发明专利
    未知

    公开(公告)号：ES2137909T1

    公开(公告)日：2000-01-01

    申请号：ES97933270

    申请日：1997-06-27

    Applicant: INTERDIGITAL TECH CORP

    Inventor： REGIS ROBERT T

    IPC: G06F13/374 ,  H04B1/7075 ,  G06F13/376 ,  H04B1/708

    Abstract: A parallel packetized intermodule arbitrated high speed control data bus system which allows high speed communications between microprocessor modules in a more complex digital processing environment. The system features a simplified hardware architecture featuring fast FIFO queuing operating at 12.5 MHz, TTL CMOS compatible level clocking signals, single bus master arbitration, synchronous clocking, DMA, and unique module addressing for multiprocessor systems. The system includes a parallel data bus with sharing bus masters residing on each processing module decreeing the communication and data transfer protocols. Bus arbitration is performed over a dedicated serial arbitration line and each requesting module competes for access to the parallel data bus by placing the address of the requesting module on the arbitration line and monitoring the arbitration line for collisions.

    EFFICIENT MULTICHANNEL FILTERING FOR CDMA MODEMS
    9.
    发明专利
    EFFICIENT MULTICHANNEL FILTERING FOR CDMA MODEMS 未知

    公开(公告)号：HK1017175A1

    公开(公告)日：1999-11-12

    申请号：HK99102017

    申请日：1999-05-05

    Applicant: INTERDIGITAL TECH CORP

    Inventor： REGIS ROBERT T

    IPC: G06F17/10 ,  H03H17/02 ,  H03H17/06 ,  H04B1/707 ,  H04B1/7075 ,  H04B1/708 ,  H04B1/7093 ,  H04B7/216 ,  H03H

    Abstract: The present invention provides a multichannel digital filter for filtering a plurality of signals transmitted via a plurality of channels in a code division multiple access (CDMA) communication system, the multichannel digital filter comprising: a plurality of filter inputs, one for each of the plurality of channels; a filter output for generating a single filter output for the plurality of filter inputs from the plurality of channels; a plurality of look-up tables (LUTs), each LUT comprising a plurality of memory addresses, for storing respective ones of precomputed weighted sums for all possible combinations of the plurality of filter inputs, whereby each LUT outputs a weighted sum of the plurality of filter inputs in accordance with the filter inputs from the plurality of channels; and a plurality of registers and a plurality of adders alternately arranged in series, whereby each adder adds outputs of the LUT and the value stored in each register in each operation cycle and each register buffers the output of each adder temporarily until the next operation cycle.

    Parallel packetized intermodule arbitrated high speed control and data bus
    10.
    发明专利
    Parallel packetized intermodule arbitrated high speed control and data bus 未知

    公开(公告)号：AU3649597A

    公开(公告)日：1998-01-14

    申请号：AU3649597

    申请日：1997-06-27

    Applicant: INTERDIGITAL TECH CORP

    Inventor： REGIS ROBERT T

    IPC: G06F13/376 ,  G06F13/374 ,  H04B1/7075 ,  H04B1/708

    Abstract: A parallel packetized intermodule arbitrated high speed control data bus system which allows high speed communications between microprocessor modules in a more complex digital processing environment. The system features a simplified hardware architecture featuring fast FIFO queuing operating at 12.5 MHz, TTL CMOS compatible level clocking signals, single bus master arbitration, synchronous clocking, DMA, and unique module addressing for multiprocessor systems. The system includes a parallel data bus with sharing bus masters residing on each processing module decreeing the communication and data transfer protocols. Bus arbitration is performed over a dedicated serial arbitration line and each requesting module competes for access to the parallel data bus by placing the address of the requesting module on the arbitration line and monitoring the arbitration line for collisions.

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