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    Electronic device and method of manufacturing electronic device
    3.
    发明授权
    Electronic device and method of manufacturing electronic device 有权

    公开(公告)号：US12211811B2

    公开(公告)日：2025-01-28

    申请号：US17702812

    申请日：2022-03-24

    Applicant: Industrial Technology Research Institute

    Inventor： Yu-Ming Peng ,  Chien-Chou Tseng ,  Chih-Chia Chang ,  Kuan-Chu Wu ,  Yu-Lin Hsu

    IPC: H01L23/00 ,  H01L21/66 ,  H01L23/13 ,  H01L23/14 ,  H01L33/62

    Abstract: An electronic device includes a substrate, an electronic component, a first interposing layer and a second interposing layer. The substrate is non-planar and the substrate includes a first substrate pad and a second substrate pad. The electronic component includes a first component pad and a second component pad corresponding to the first substrate pad and the second substrate pad respectively. When the first component pad contacts the first substrate pad, a height difference exists between the second component pad and the second substrate pad. The first interposing layer connects between the first component pad and the first substrate pad. The second interposing layer connects between the second component pad and the second substrate pad. A thickness difference between the first interposing layer and the second interposing layer is 0.5 to 1 time the height difference.

    FLEXIBLE ELECTRONIC DEVICE
    4.
    发明公开
    FLEXIBLE ELECTRONIC DEVICE 审中-公开

    公开(公告)号：US20240341653A1

    公开(公告)日：2024-10-17

    申请号：US18420789

    申请日：2024-01-24

    Applicant: Industrial Technology Research Institute

    Inventor： Min-Hsiung Liang ,  Chien-Hsun Chu ,  Kuan-Chu Wu ,  Wan-Chen Yang ,  Jui-Chang Chuang ,  Chen-Tsai Yang ,  Heng-Yin Chen ,  Hung-Hsien Ko

    IPC: A61B5/263

    CPC classification number: A61B5/263 ,  A61B2562/164 ,  A61B2562/18

    Abstract: A flexible electronic device includes a first encapsulation layer and a sensing structure. The sensing structure is disposed on the first encapsulation layer and includes a substrate, a plurality of first sensing layer, a plurality of second sensing layer, a first groove and a second groove. The substrate includes a main body, a plurality of first branches and a plurality of second branches. The main body has a first side and a second side opposite to each other. The first branches connect the first side. The second branches connect the second side. The first sensing layers are disposed on the first branches. The second sensing layers are disposed on the second branches. The first groove is disposed between the first branches. The second groove is disposed between the second branches.

    CHIP PACKAGE STRUCTURE
    5.
    发明申请
    CHIP PACKAGE STRUCTURE 有权

    公开(公告)号：US20210183789A1

    公开(公告)日：2021-06-17

    申请号：US16792905

    申请日：2020-02-18

    Applicant: Industrial Technology Research Institute

    Inventor： Te-Hsun Lin ,  Chen-Tsai Yang ,  Kuan-Chu Wu ,  Shao-An Yan

    IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538

    Abstract: A chip package structure including a substrate, a redistribution layer (RDL), a chip and an encapsulant is provided. The RDL is disposed on the substrate. The chip is disposed on the RDL and is electrically connected with the RDL. The encapsulant is disposed on the RDL and encapsulates the chip. The chip is located in the high stress region. From a top view, the chip is located in the high stress region, and the low stress region surrounds the high stress region. The RDL includes at least one first device located in the high stress region. From the top view, the extending direction of the at least one first device is parallel to a stress direction at a position thereof.

    Chip package structure
    7.
    发明授权
    Chip package structure 有权

    公开(公告)号：US11362045B2

    公开(公告)日：2022-06-14

    申请号：US16792905

    申请日：2020-02-18

    Applicant: Industrial Technology Research Institute

    Inventor： Te-Hsun Lin ,  Chen-Tsai Yang ,  Kuan-Chu Wu ,  Shao-An Yan

    IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/14 ,  H01L23/498

    Abstract: A chip package structure including a substrate, a redistribution layer (RDL), a chip and an encapsulant is provided. The RDL is disposed on the substrate. The chip is disposed on the RDL and is electrically connected with the RDL. The encapsulant is disposed on the RDL and encapsulates the chip. The chip is located in the high stress region. From a top view, the chip is located in the high stress region, and the low stress region surrounds the high stress region. The RDL includes at least one first device located in the high stress region. From the top view, the extending direction of the at least one first device is parallel to a stress direction at a position thereof.

    Flexible hybrid electronic system and method of reducing the impact thereof
    8.
    发明授权
    Flexible hybrid electronic system and method of reducing the impact thereof 有权

    公开(公告)号：US10757804B1

    公开(公告)日：2020-08-25

    申请号：US16815031

    申请日：2020-03-11

    Applicant: Industrial Technology Research Institute

    Inventor： Yu-Ming Peng ,  Kuan-Chu Wu ,  Kai-Ming Chang ,  Chen-Tsai Yang

    IPC: H05K1/11 ,  H05K1/02 ,  H01L23/498

    Abstract: A flexible hybrid electronic (FHE) system includes a carrier, a first redistribution structure on the carrier, a first device on the first redistribution structure, and an encapsulation layer encapsulating the first device. The carrier has a first Young's modulus Y1. The first redistribution structure has a second Young's modulus Y2. The first device and a portion of the encapsulation layer form a top surface of the first redistribution structure to a top surface of the first device is a first portion having a third Young's modulus Y3. The other portion of the encapsulation layer from the top surface of the first device to a top surface of the encapsulation layer is a second portion having a fourth Young's modulus Y4. A ratio of Y3/Y4 is between 1.62 and 1.98; a ratio of Y3/Y2 is between 0.18 and 0.22; and a ratio of Y3/Y1 is between 280.62 and 342.98.

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