Coarse-fine counting architecture for a VCO-ADC based on interlocked binary asynchronous counters

    公开(公告)号:US11356112B1

    公开(公告)日:2022-06-07

    申请号:US17159833

    申请日:2021-01-27

    Abstract: An analog-to-digital converter includes a voltage-controlled oscillator (VCO) having an input for receiving an analog input signal; a double binary counter having a first input coupled to a first output of the VCO, a second input coupled to a second output of the VCO; a first set of registers coupled to the first output of the double binary counter; a second set of registers coupled to the second output of the double binary counter; sense amplifiers coupled to the outputs of the VCO; and a correction component coupled to the first set of registers, the second set of registers, and the sense amplifiers, wherein the correction component generates a coarse count, a fine count, and combines the coarse count and the fine count to provide a digital output signal representative of the analog input signal.

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