公开(公告)号：US20230315630A1

公开(公告)日：2023-10-05

申请号：US17708435

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Hanna Alam ,  Yuval Bustan ,  Tomer Exterman ,  Dor Kahana ,  Larisa Novakovsky ,  Joseph Nuzman

IPC: G06F12/0811

CPC classification number: G06F12/0811 ,  G06F2212/62

Abstract: Methods and apparatus relating to a dynamic inclusive and non-inclusive caching policy are described. In an embodiment, a first cache has a higher level than a second cache. Circuitry determines a caching policy between the first cache and the second cache based on a comparison of a number of active processor cores and a threshold value. The caching policy is one of an inclusive caching policy or a non-inclusive caching policy. Other embodiments are also disclosed and claimed.

公开(公告)号：US20250004536A1

公开(公告)日：2025-01-02

申请号：US18216456

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Adwait Purandare ,  Ankush Varma ,  Nilanjan Palit ,  Yuval Bustan ,  Eran Barnett ,  Eliezer Weissman ,  Stanley Chen ,  Arjan Van De Ven

IPC: G06F1/3296 ,  G06F1/324

Abstract: Techniques and mechanisms for determining operation a processor core which is in a common power delivery domain with one or more other processor cores. In an embodiment, an execution of instructions by a first core of a processor module is selectively throttled based on the detection of a single violation condition. The throttling is performed while the cores of the processor module are each maintained in a current power state. The single violation condition comprises a violation of a test criteria by the first core, while the one or more other cores of the module each satisfy the test criteria. In the case of a multiple violation condition, each core of the processor module is transitioned from one power state to another power state. In another embodiment, the test criteria includes or is otherwise based on a threshold level of a dynamic capacitance for a given core.