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公开(公告)号:US20250130848A1
公开(公告)日:2025-04-24
申请号:US18934573
申请日:2024-11-01
Applicant: Intel Corporation
Inventor: Vasanth Ranganathan , James Valerio , Joydeep Ray , Abhishek R. Appu , Alan Curtis , Prathamesh Raghunath Shinde , Brandon Fliflet , Ben J. Ashbaugh , John Wiegert
Abstract: An apparatus to facilitate barrier state save and restore for preemption in a graphics environment is disclosed. The apparatus includes processing resources to execute a plurality of execution threads that are comprised in a thread group (TG) and mid-thread preemption barrier save and restore hardware circuitry to: initiate an exception handling routine in response to a mid-thread preemption event, the exception handling routine to cause a barrier signaling event to be issued; receive indication of a valid designated thread status for a thread of a thread group (TG) in response to the barrier signaling event; and in response to receiving the indication of the valid designated thread status for the thread of the TG, cause, by the thread of the TG having the valid designated thread status, a barrier save routine and a barrier restore routine to be initiated for named barriers of the TG.
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公开(公告)号:US20220413899A1
公开(公告)日:2022-12-29
申请号:US17358882
申请日:2021-06-25
Applicant: Intel Corporation
Inventor: Vasanth Ranganathan , James Valerio , Joydeep Ray , Abhishek R. Appu , Alan Curtis , Prathamesh Raghunath Shinde , Brandon Fliflet , Ben J. Ashbaugh , John Wiegert
Abstract: An apparatus to facilitate barrier state save and restore for preemption in a graphics environment is disclosed. The apparatus includes processing resources to execute a plurality of execution threads that are comprised in a thread group (TG) and mid-thread preemption barrier save and restore hardware circuitry to: initiate an exception handling routine in response to a mid-thread preemption event, the exception handling routine to cause a barrier signaling event to be issued; receive indication of a valid designated thread status for a thread of a thread group (TG) in response to the barrier signaling event; and in response to receiving the indication of the valid designated thread status for the thread of the TG, cause, by the thread of the TG having the valid designated thread status, a barrier save routine and a barrier restore routine to be initiated for named barriers of the TG.
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公开(公告)号:US20250147762A1
公开(公告)日:2025-05-08
申请号:US18504407
申请日:2023-11-08
Applicant: Intel Corporation
Inventor: Vasanth Ranganathan , Gang Chen , Supratim Pal , Jorge Eduardo Parra Osorio , Arthur Hunter , Boris Kuznetsov , Deepak N K , Siva Kumar Seemakurthi , James Valerio , Shubham Dinesh Chavan , Abhishek Kumar Singh , Samir Pandya , Sandeep Tippannanavar Niranjan , Alan Curtis , Jain Philip , Maltesh Kulkarni , Fangwen Fu , John Wiegert , Brent Schwartz
Abstract: Described herein is a graphics processor having processing resources with configurable thread and register configurations. Program code can configure a number of registers and accumulators that will be used by hardware threads during execution of the program code by the graphics processor. Processing resources within the graphics processor can be configured to assign different numbers of registers and accumulators to hardware threads based on the configuration requested by program code to be executed by the processing resource.
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公开(公告)号:US12164952B2
公开(公告)日:2024-12-10
申请号:US17358882
申请日:2021-06-25
Applicant: Intel Corporation
Inventor: Vasanth Ranganathan , James Valerio , Joydeep Ray , Abhishek R. Appu , Alan Curtis , Prathamesh Raghunath Shinde , Brandon Fliflet , Ben J. Ashbaugh , John Wiegert
Abstract: An apparatus to facilitate barrier state save and restore for preemption in a graphics environment is disclosed. The apparatus includes processing resources to execute a plurality of execution threads that are comprised in a thread group (TG) and mid-thread preemption barrier save and restore hardware circuitry to: initiate an exception handling routine in response to a mid-thread preemption event, the exception handling routine to cause a barrier signaling event to be issued; receive indication of a valid designated thread status for a thread of a thread group (TG) in response to the barrier signaling event; and in response to receiving the indication of the valid designated thread status for the thread of the TG, cause, by the thread of the TG having the valid designated thread status, a barrier save routine and a barrier restore routine to be initiated for named barriers of the TG.
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