公开(公告)号：US10732880B2

公开(公告)日：2020-08-04

申请号：US15868787

申请日：2018-01-11

Applicant: Intel Corporation

Inventor： Omid Azizi ,  Amin Firoozshahian ,  John Stevenson ,  Mahesh Maddury ,  Chandan Egbert ,  Henk Neefs

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0868

Abstract: Various systems and methods for computer memory management are described herein. A system for computer memory management includes a first memory device including a mapping table; a second memory device including a staging area; a third memory device including a dedup data region; and a controller operable to: receive a memory access request, the memory access request including an address and data; write the data to the staging area; and update the mapping table with the address.

公开(公告)号：US20220179797A1

公开(公告)日：2022-06-09

申请号：US17682111

申请日：2022-02-28

Applicant: Intel Corporation

Inventor： Jeffrey C. Swanson ,  Sreenivas Mandava ,  Henk Neefs ,  Jing Ling

IPC: G06F12/0888 ,  G06F12/1018 ,  G06F9/46 ,  G06F9/48

Abstract: An embodiment of an apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to control access to a memory, convert an address for a transaction for the memory from a first address in a first address space to a second address in a second address space, determine a bandwidth bypass condition for the transaction based on a bandwidth of memory transactions for the memory, and provide the second address for the transaction to a scheduler at a time based at least in part on the determined bandwidth bypass condition. Other embodiments are disclosed and claimed.