公开(公告)号：US20230315470A1

公开(公告)日：2023-10-05

申请号：US17708933

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Matthew Merten ,  Beeman Strong ,  Moshe Cohen ,  Ahmad Yasin ,  Andreas Kleen ,  Stanislav Bratanov ,  Karthik Gopalakrishnan ,  Angela Schmid ,  Grant Zhou

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32 ,  G06F11/34

CPC classification number: G06F9/3814 ,  G06F9/30101 ,  G06F9/321 ,  G06F11/3409

Abstract: Techniques and mechanisms for configuring processor event-based sampling (PEBS) with a set of control registers. In an embodiment, a first control register of a processor is programmed to store a physical address of a location in a buffer which receives PEBS records. The first control register is further programmed or otherwise configured to store an indication of a size of the buffer. A second control register of the processor stores a physical address of a location in the buffer were a next PEBS record is to be stored. In another embodiment, the processor further comprises multiple control registers which variously configure PEBS generation on a per-counter basis.

公开(公告)号：US20240111654A1

公开(公告)日：2024-04-04

申请号：US18374296

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Raoul Rivas Toledano ,  Udayan Kapaley ,  Ahmad Yasin ,  Karthik Gopalakrishnan ,  Marc Torrant

IPC: G06F11/34 ,  G06F9/30

CPC classification number: G06F11/3466 ,  G06F9/30145 ,  G06F11/3409

Abstract: Detailed herein are examples of hybrid (heterogenous) performance monitoring unit enumeration. In some examples, a processor supports an instruction that enumerates performance monitoring unit enumeration. For example, the processor comprises decoder circuitry to decode an instance of a single instruction, the single instruction to include a field for an opcode; and execution circuitry to execute the decoded instruction according to the opcode to return the processor identification and feature information including an enumeration of heterogenous performance monitoring unit capabilities.