公开(公告)号：US20240330146A1

公开(公告)日：2024-10-03

申请号：US18194400

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Moshe Cohen ,  Ahmad Yasin

IPC: G06F11/34

CPC classification number: G06F11/3495 ,  G06F11/3409

Abstract: Techniques for snapshotting of performance monitoring are described. In an embodiment, an apparatus includes a plurality of performance monitoring hardware resources, hardware to capture a record of state data related to state of the apparatus in connection with an occurrence of an event, and storage to store a first indicator corresponding to at least a first performance monitoring hardware resource of the plurality of performance monitoring hardware resources and to enable the hardware to include, in the record, performance data from the first performance monitoring hardware resource.

公开(公告)号：US20190205061A1

公开(公告)日：2019-07-04

申请号：US15858878

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Alexander Gendler ,  Efraim Rotem ,  Moshe Cohen ,  Asit K. Mallick ,  Jason W. Brandt ,  Kameswar Subramaniam ,  Nathan Fellman ,  Hisham Shafi

IPC: G06F3/06 ,  G06F9/30

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0673 ,  G06F9/30098 ,  G06F9/4406 ,  G06F9/45558 ,  G06F2009/45583

Abstract: Processor, method, and system for reducing latency in accessing remote registers is described herein. One embodiment of a processor includes one or more remote registers and remote register access circuitry. The remote register access circuitry is to detect a request from the requestor to access a first register of the one or more remote registers, access to the first register in accordance to the request without the requestor having to wait for completion of the access, and provide a notification accessible to the requestor upon completion of the access to the first register of the one or more remote registers.

公开(公告)号：US20230315470A1

公开(公告)日：2023-10-05

申请号：US17708933

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Matthew Merten ,  Beeman Strong ,  Moshe Cohen ,  Ahmad Yasin ,  Andreas Kleen ,  Stanislav Bratanov ,  Karthik Gopalakrishnan ,  Angela Schmid ,  Grant Zhou

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32 ,  G06F11/34

CPC classification number: G06F9/3814 ,  G06F9/30101 ,  G06F9/321 ,  G06F11/3409

Abstract: Techniques and mechanisms for configuring processor event-based sampling (PEBS) with a set of control registers. In an embodiment, a first control register of a processor is programmed to store a physical address of a location in a buffer which receives PEBS records. The first control register is further programmed or otherwise configured to store an indication of a size of the buffer. A second control register of the processor stores a physical address of a location in the buffer were a next PEBS record is to be stored. In another embodiment, the processor further comprises multiple control registers which variously configure PEBS generation on a per-counter basis.

公开(公告)号：US10909015B2

公开(公告)日：2021-02-02

申请号：US15396293

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Ahmad Yasin ,  Moshe Cohen ,  Jacob Jack Doweck

IPC: G06F11/30 ,  G06F9/46 ,  G06F11/34

Abstract: An apparatus and method are described for generating performance metrics of a processor. For example, one embodiment of a processor comprises: one or more simultaneous multithreading cores to simultaneously execute multiple instruction threads; a plurality of performance monitor counters, each to maintain a count of events occurring as a result of the execution of the multiple instruction threads; and a performance monitor unit to generate a plurality of performance metric values using the event counts stored in the performance monitor counters and in response to receipt of a request from software for the performance metric values.