公开(公告)号：US20220093316A1

公开(公告)日：2022-03-24

申请号：US17029870

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Benjamin Duong ,  Michael Garelick ,  Darko Grujicic ,  Tarek Ibrahim ,  Brandon C. Marin ,  Sai Vadlamani ,  Marcel Wall

IPC: H01F27/28 ,  H01L23/64 ,  H01F41/32 ,  H01L23/498

Abstract: An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.

公开(公告)号：US20240331921A1

公开(公告)日：2024-10-03

申请号：US18739049

申请日：2024-06-10

Applicant: Intel Corporation

Inventor： Benjamin Duong ,  Michael Garelick ,  Darko Grujicic ,  Tarek Ibrahim ,  Brandon C. Marin ,  Sai Vadlamani ,  Marcel Wall

IPC: H01F27/28 ,  H01F41/32 ,  H01L23/498 ,  H01L23/64

CPC classification number: H01F27/2804 ,  H01F41/32 ,  H01L23/49827 ,  H01L23/645 ,  H01F2027/2809 ,  H01L23/49816

Abstract: An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.

公开(公告)号：US12057252B2

公开(公告)日：2024-08-06

申请号：US17029870

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Benjamin Duong ,  Michael Garelick ,  Darko Grujicic ,  Tarek Ibrahim ,  Brandon C. Marin ,  Sai Vadlamani ,  Marcel Wall

IPC: H05K1/02 ,  H01F1/37 ,  H01F17/04 ,  H01F17/06 ,  H01F27/24 ,  H01F27/245 ,  H01F27/28 ,  H01F27/29 ,  H01F41/24 ,  H01F41/32 ,  H01L23/15 ,  H01L23/498 ,  H01L23/64 ,  H05K1/09 ,  H05K3/02 ,  H05K3/42

CPC classification number: H01F27/2804 ,  H01F41/32 ,  H01L23/49827 ,  H01L23/645 ,  H01F2027/2809 ,  H01L23/49816

Abstract: An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.