公开(公告)号：WO2015047630A1

公开(公告)日：2015-04-02

申请号：PCT/US2014/052746

申请日：2014-08-26

Applicant: INTEL CORPORATION ,  PANGAL, Kiran ,  RAMANUJAN, Raj K. ,  FABER, Robert W. ,  SUNDARAM, Rajesh

Inventor： PANGAL, Kiran ,  RAMANUJAN, Raj K. ,  FABER, Robert W. ,  SUNDARAM, Rajesh

IPC: G11C13/00 ,  G11C11/21

CPC classification number: G11C13/0033 ,  G11C13/0004 ,  G11C2013/0076

Abstract: Embodiments including systems, methods, and apparatuses associated with refreshing memory cells are disclosed herein. In embodiments, a memory controller may be configured to perform a read operation on one or more memory cells in a cross-point non-volatile memory such as a phase change memory (PCM). The one or more memory cells may have voltage values respectively set to a first threshold voltage or a second threshold voltage. Based on the read, the memory controller may identify the memory cells in the cross-point non-volatile memory that are set to the second threshold voltage, and refresh the voltage values of those cells without altering the voltage values of the memory cells in the cross-point non-volatile memory that are set to the first threshold voltage. Other embodiments may be described or claimed.

Abstract translation: 本文公开了包括与刷新存储器单元相关联的系统，方法和装置的实施例。 在实施例中，存储器控制器可以被配置为对诸如相变存储器（PCM）的交叉点非易失性存储器中的一个或多个存储器单元执行读取操作。 一个或多个存储单元可以具有分别设置为第一阈值电压或第二阈值电压的电压值。 基于读取，存储器控制器可以识别被设置为第二阈值电压的交叉点非易失性存储器中的存储器单元，并且在不改变这些存储器单元的电压值的情况下刷新那些单元的电压值 交叉点非易失性存储器被设置为第一阈值电压。 可以描述或要求保护其他实施例。

公开(公告)号：WO2003052567A2

公开(公告)日：2003-06-26

申请号：PCT/US2002/038707

申请日：2002-12-02

Applicant: INTEL CORPORATION

Inventor： SUNDARAM, Rajesh ,  JAVANIFARD, Jahanshir

IPC: G06F1/26

CPC classification number: G11C16/30 ,  G11C16/12

Abstract: A system includes a processor and a flash memory block that may receive an operating voltage sufficient for reading a memory cell. A standby oscillator may generate a first signal to a Power-Supply-In-Package block and a second, higher frequency signal to a regulator block. The first signal may control the time at which charge is stored on a first capacitor that may be used to provide charge in a standby mode to a second capacitor. The second signal may control the time at which charge is stored on the second capacitor.

Abstract translation: 系统包括处理器和闪存块，其可以接收足以读取存储器单元的工作电压。 备用振荡器可以产生到电源包装块的第一信号，以及向调节器块产生第二较高频率信号。 第一信号可以控制在第一电容器上存储电荷的时间，第一电容器可用于在待机模式下向第二电容器提供电荷。 第二信号可以控制在第二电容器上存储电荷的时间。

公开(公告)号：WO2017172283A1

公开(公告)日：2017-10-05

申请号：PCT/US2017/020989

申请日：2017-03-06

Applicant: INTEL CORPORATION

Inventor： QAWAMI, Shekoufeh ,  SUNDARAM, Rajesh ,  DAMLE, Prashant S. ,  RIVERS, Doyle ,  WALKER, Julie M.

IPC: G06F13/16

CPC classification number: G11C13/0033 ,  G06F13/1668 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069

Abstract: Apparatus, systems, and methods to correct for threshold voltage drift in non- volatile memory devices are disclosed and described. In one example, a compensated demarcation voltage is generated by either a time-based drift compensation scheme or a disturb-based drift compensation scheme, and read and write operations to the non- volatile memory are carried out using the compensated voltage threshold.

Abstract translation: 公开并描述了用于校正非易失性存储器设备中的阈值电压漂移的设备，系统和方法。 在一个示例中，通过基于时间的漂移补偿方案或基于干扰的漂移补偿方案来生成补偿的分界电压，并且使用补偿的电压阈值来执行对非易失性存储器的读取和写入操作。 p>

公开(公告)号：WO2017034726A1

公开(公告)日：2017-03-02

申请号：PCT/US2016/043910

申请日：2016-07-25

Applicant: INTEL CORPORATION

Inventor： SUNDARAM, Rajesh ,  SWAMINATHAN, Muthukumar P. ,  RIVERS, Doyle

IPC: G06F1/20 ,  G06F1/16

CPC classification number: G06F1/206 ,  G06F1/3225 ,  G06F1/3275

Abstract: Data reliability and integrity may be compromised when memory resources used to store the data reach elevated temperatures. A sensor in the memory resource may monitor the temperature of the memory resource in real-time. A comparator in the memory resource may indicate a high temperature condition to a memory controller. The memory controller, in response to the high temperature condition, can restrict or halt data flow to the memory resource. When the real-time temperature of the memory resource falls below a defined threshold, the memory controller may resume data flow to the memory resource.

Abstract translation: 当用于存储数据的内存资源达到升高的温度时，数据的可靠性和完整性可能会受到影响。 存储器资源中的传感器可以实时监视存储器资源的温度。 存储器资源中的比较器可以向存储器控制器指示高温状态。 存储器控制器响应于高温条件，可以限制或停止到存储器资源的数据流。 当存储器资源的实时温度低于定义的阈值时，存储器控制器可以恢复到存储器资源的数据流。

公开(公告)号：WO2017052731A1

公开(公告)日：2017-03-30

申请号：PCT/US2016/042866

申请日：2016-07-18

Applicant: INTEL CORPORATION

Inventor： JAYACHANDRAN, Sowmiya ,  SUNDARAM, Rajesh ,  FABER, Robert

IPC: G06F1/32 ,  G06F12/02

CPC classification number: G06F3/0625 ,  G06F1/3275 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/02 ,  G11C5/147 ,  G11C5/148 ,  G11C7/00 ,  Y02D10/14

Abstract: Examples are given for techniques for entry to a lower power state for a memory device or die. The examples to include delaying transitions of the memory device or die from a first higher consuming power state to a second relatively lower power state using one or more programmable counters maintained at or with the memory device.

Abstract translation: 给出了用于进入存储器件或管芯的较低功率状态的技术的示例。 这些示例包括使用保存在存储器设备处或与存储器设备一起的一个或多个可编程计数器来将存储器件或管芯从第一较高功耗状态延迟转换到第二较低功率状态的示例。

公开(公告)号：WO2012067871A2

公开(公告)日：2012-05-24

申请号：PCT/US2011/059529

申请日：2011-11-07

Applicant: INTEL CORPORATION ,  SUNDARAM, Rajesh ,  KAU, Derchang ,  ZIMMERMAN, David J.

Inventor： SUNDARAM, Rajesh ,  KAU, Derchang ,  ZIMMERMAN, David J.

IPC: G11C13/02

CPC classification number: G11C13/0004 ,  G06F2213/0038 ,  G11C7/1039 ,  G11C13/0061 ,  G11C13/0069

Abstract: An apparatus for data storage is presented. In one embodiment, the apparatus includes a phase change memory device comprising phase change memory storage elements. The apparatus further includes control logic to control two or more set pipelines to serve memory requests in a staggered manner, such that set operations of the memory requests begin at different times.

Abstract translation: 提出了一种用于数据存储的设备。 在一个实施例中，该装置包括包括相变存储器存储元件的相变存储器件。 该装置还包括控制逻辑以控制两个或更多个集合管线以交错方式提供存储器请求，使得存储器请求的设置操作在不同时间开始。

公开(公告)号：WO2003052910A1

公开(公告)日：2003-06-26

申请号：PCT/US2002/038710

申请日：2002-12-02

Applicant: INTEL CORPORATION

Inventor： SUNDARAM, Rajesh ,  JAVANIFARD, Jahanshir

IPC: H02M3/157

CPC classification number: H02M3/157 ,  G11C16/30 ,  H02M2001/0032 ,  Y02B70/16

Abstract: Variable voltage source (80) for a flash memory device. The variable voltage source (80) receives an input voltage (V) and provides an output voltage (Vout) for a read or write operations in the flash memory. The variable voltage source (80) further comprises a voltage-divider (170, 180, 190, 200) and a tap circuit (210) for selecting a tap point, according to the received data values in the control logic (230). The voltage selected from the tap point is compared with the voltage reference in the regulation circuit (220), which controls a transistor (150) for switching the output current flowing through the inductor (130).

Abstract translation: 闪存器件的可变电压源（80）。 可变电压源（80）接收输入电压（V）并提供用于闪存中的读或写操作的输出电压（Vout）。 可变电压源（80）还包括根据控制逻辑（230）中接收到的数据值的分压器（170,180,190,200）和抽头电路（210），用于选择抽头点。 从分接点选择的电压与调节电路（220）中的电压基准值进行比较，调节电路（220）控制用于切换流过电感器（130）的输出电流的晶体管（150）。

公开(公告)号：WO2002080182A2

公开(公告)日：2002-10-10

申请号：PCT/US2002/008751

申请日：2002-03-21

Applicant: INTEL CORPORATION

Inventor： TEDROW, Kerry ,  SUNDARAM, Rajesh

IPC: G11C16/00

CPC classification number: G11C16/12 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30

Abstract: The present invention is in the field of flash memory. More particularly, embodiments of the present invention may provide a negative voltage for erasing when coupled to a memory cell to be erased and provide voltages to read or program when not coupled to a memory cell that is selected to be erased. Embodiments may also provide a high magnitude negative voltage to erase; a low impedance, low voltage current to read or program; and burn little to no current when not couplet to a memory cell that is selected to be erased.

Abstract translation: 本发明在闪速存储器领域。 更具体地，本发明的实施例可以提供用于擦除的负电压，用于当被擦除的存储器单元耦合到待擦除的存储器单元时提供擦除的电压，并且当未耦合到被选择要擦除的存储器单元时提供读取或编程的电压。 实施例还可以提供高幅度的负电压来擦除; 低阻抗，低电压电流读取或编程; 并且当不连接到被选择被擦除的存储器单元时，几乎没有电流烧坏。

公开(公告)号：WO2018063728A1

公开(公告)日：2018-04-05

申请号：PCT/US2017/049502

申请日：2017-08-30

Applicant: INTEL CORPORATION

Inventor： SUNDARAM, Rajesh ,  FAZIO, Albert ,  KAU, Derchang ,  QAWAMI, Shekoufeh

IPC: G06F13/16 ,  G11C13/00

Abstract: Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.

Abstract translation: 公开并描述了交叉点存储器体系结构，设备，系统和方法，并且可以包括具有可扩展的增加的带宽的交叉点存储器核心子系统。 存储器核心可以包括多个独立操作的分区，每个分区包括多个交叉点存储器阵列。

公开(公告)号：WO2017112320A1

公开(公告)日：2017-06-29

申请号：PCT/US2016/063687

申请日：2016-11-23

Applicant: INTEL CORPORATION

Inventor： QAWAMI, Shekoufeh ,  ALLEN, Michael ,  SUNDARAM, Rajesh

IPC: G11C7/22 ,  H03L7/081

CPC classification number: G11C7/222 ,  G06F13/1689 ,  G11C29/022 ,  G11C29/023 ,  G11C29/1201 ,  G11C29/12015 ,  G11C2207/2254

Abstract: A memory device performs DLL (delay locked loop) calibration in accordance with a DLL calibration mode configured for the memory device. A host controller can configure the calibration mode based on operating conditions for the memory device. The memory device includes an input/output (I/O) interface circuit and a delay locked loop (DLL) circuit coupled to control I/O timing of the I/O interface. A control circuit of the memory device selectively enables and disables DLL calibration in accordance with the DLL calibration mode. When selectively enabled, the DLL calibration is to operate at a time interval identified by the DLL calibration mode, and when selectively disabled, the DLL calibration is to cease or refrain from DLL calibration operations.

Abstract translation: 存储器件根据为存储器件配置的DLL校准模式执行DLL（延迟锁定环）校准。 主机控制器可以基于存储器设备的操作条件来配置校准模式。 存储器装置包括输入/​​输出（I / O）接口电路和被耦合以控制I / O接口的I / O定时的延迟锁定环（DLL）电路。 存储器设备的控制电路根据DLL校准模式选择性地启用和禁用DLL校准。 选择性启用时，DLL校准将在由DLL校准模式识别的时间间隔内运行，并且当选择性禁用时，DLL校准将停止或避免DLL校准操作。