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    SCALABLE BANDWIDTH NON-VOLATILE MEMORY
    2.
    发明申请
    SCALABLE BANDWIDTH NON-VOLATILE MEMORY 审中-公开
    可扩展的带宽非易失性存储器

    公开(公告)号：WO2018063728A1

    公开(公告)日：2018-04-05

    申请号：PCT/US2017/049502

    申请日：2017-08-30

    Applicant: INTEL CORPORATION

    Inventor： SUNDARAM, Rajesh ,  FAZIO, Albert ,  KAU, Derchang ,  QAWAMI, Shekoufeh

    IPC: G06F13/16 ,  G11C13/00

    Abstract: Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.

    Abstract translation: 公开并描述了交叉点存储器体系结构，设备，系统和方法，并且可以包括具有可扩展的增加的带宽的交叉点存储器核心子系统。 存储器核心可以包括多个独立操作的分区，每个分区包括多个交叉点存储器阵列。

    DOUBLE-PULSE WRITE FOR PHASE CHANGE MEMORY
    3.
    发明申请
    DOUBLE-PULSE WRITE FOR PHASE CHANGE MEMORY 审中-公开
    双相脉冲写入相变存储器

    公开(公告)号：WO2011059576A2

    公开(公告)日：2011-05-19

    申请号：PCT/US2010/050137

    申请日：2010-09-24

    Applicant: INTEL CORPORATION ,  KAU, Derchang ,  KALB, Johannes ,  KLEHN, Brett

    Inventor： KAU, Derchang ,  KALB, Johannes ,  KLEHN, Brett

    CPC classification number: G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0052 ,  G11C2013/008 ,  G11C2013/0092

    Abstract: The present invention discloses a method including: writing a phase change material from a high RESET state to a weakened RESET state with a first step; writing the phase change material from the weakened RESET state to a SET state with a second step, the second step having a lower current than the first step; verifying a parameter of the phase change material wherein if the parameter is higher than a target for a SET state, then repeating the writing with the first step, the writing with the second step, and the verifying until the parameter is lower than the target wherein a current for the first step is decreased by a decrement with each iteration without becoming lower than a current for the second step.

    Abstract translation: 本发明公开了一种方法，包括：利用第一步骤将相变材料从高RESET状态写入减弱的RESET状态; 用第二步将相变材料从减弱的RESET状态写入SET状态，第二步具有比第一步低的电流; 验证相变材料的参数，其中如果参数高于SET状态的目标，则重复第一步的写入，第二步的写入和验证，直到参数低于目标 第一步的电流在每次迭代时递减一个递减量，而不低于第二步的电流。

    REFERENCE ARCHITECTURE IN A CROSS-POINT MEMORY
    6.
    发明申请
    REFERENCE ARCHITECTURE IN A CROSS-POINT MEMORY 审中-公开
    跨点存储器中的参考架构

    公开(公告)号：WO2015199829A1

    公开(公告)日：2015-12-30

    申请号：PCT/US2015/030585

    申请日：2015-05-13

    Applicant: INTEL CORPORATION

    Inventor： SRINIVASAN, Balaji ,  RIVERS, Doyle ,  KAU, Derchang ,  GOLDMAN, Matthew

    IPC: G11C13/02 ,  G11C7/10

    CPC classification number: G11C13/0004 ,  G11C7/12 ,  G11C8/08 ,  G11C11/24 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2213/77

    Abstract: The present disclosure relates to reference and sense architecture in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes word line (WL) switch circuitry configured to select a global WL (GWL) and a local WL (LWL) associated with the target memory cell; bit line (BL) switch circuitry configured to select a global BL (GBL) and a local BL (LBL) associated with the target memory cell; and sense circuitry including a first sense circuitry capacitance and a second sense circuitry capacitance, the sense circuitry configured to precharge the selected GWL, the LWL and the first sense circuitry capacitance to a WL bias voltage WLVDM, produce a reference voltage (V REF ) utilizing charge on the selected GWL and charge on the first sense circuitry capacitance and determine a state of the target memory cell based, at least in part, on V REF and a detected memory cell voltage V LWL .

    Abstract translation: 本公开涉及交叉点存储器中的参考和感测架构。 设备可以包括配置为选择用于存储器访问操作的目标存储器单元的存储器控​​制器。 存储器控制器包括被配置为选择与目标存储器单元相关联的全局WL（GWL）和本地WL（LWL）的字线（WL）开关电路; 配置为选择与目标存储器单元相关联的全局BL（GBL）和本地BL（LBL）的位线（BL）开关电路; 以及感测电路，其包括第一感测电路电容和第二感测电路电容，所述感测电路被配置为将所选择的GWL，LWL和第一感测电路电容预充电到WL偏置电压WLVDM，产生使用充电的参考电压（VREF） 在所选择的GWL上并对第一感测电路电容进行充电，并且至少部分地基于VREF和检测到的存储器单元电压VLWL来确定目标存储器单元的状态。

    DOUBLE-PULSE WRITE FOR PHASE CHANGE MEMORY
    9.
    发明公开
    DOUBLE-PULSE WRITE FOR PHASE CHANGE MEMORY 审中-公开
    双脉冲占优的相变存储器

    公开(公告)号：EP2494556A2

    公开(公告)日：2012-09-05

    申请号：EP10830375.1

    申请日：2010-09-24

    Applicant: Intel Corporation

    Inventor： KAU, Derchang ,  KALB, Johannes ,  KLEHN, Brett

    IPC: G11C16/34 ,  G11C16/20 ,  G11C13/02

    CPC classification number: G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0052 ,  G11C2013/008 ,  G11C2013/0092

    Abstract: The present invention discloses a method including: writing a phase change material from a high RESET state to a weakened RESET state with a first step; writing the phase change material from the weakened RESET state to a SET state with a second step, the second step having a lower current than the first step; verifying a parameter of the phase change material wherein if the parameter is higher than a target for a SET state, then repeating the writing with the first step, the writing with the second step, and the verifying until the parameter is lower than the target wherein a current for the first step is decreased by a decrement with each iteration without becoming lower than a current for the second step.

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