公开(公告)号：US20200328182A1

公开(公告)日：2020-10-15

申请号：US16915282

申请日：2020-06-29

Applicant: Intel IP Corporation

Inventor： Bernd WAIDHAS ,  Georg SEIDEMANN ,  Andreas WOLTER ,  Thomas WAGNER ,  Stephan Stoeckl ,  Laurent MILLOU

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L21/683

Abstract: An embedded-bridge substrate connector apparatus includes a patterned reference layer to which a first module and a subsequent module are aligned and the two modules are mated at the patterned reference layer. At least one module includes a silicon bridge connector that bridges to two devices, through the patterned reference layer, to the mated module.

公开(公告)号：US10727197B2

公开(公告)日：2020-07-28

申请号：US15464920

申请日：2017-03-21

Applicant: Intel IP Corporation

Inventor： Bernd Waidhas ,  Georg Seidemann ,  Andreas Wolter ,  Thomas Wagner ,  Stephan Stoeckl ,  Laurent Millou

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L21/683

Abstract: An embedded-bridge substrate connector apparatus includes a patterned reference layer to which a first module and a subsequent module are aligned and the two modules are mated at the patterned reference layer. At least one module includes a silicon bridge connector that bridges to two devices, through the patterned reference layer, to the mated module.

公开(公告)号：US10141265B2

公开(公告)日：2018-11-27

申请号：US15394388

申请日：2016-12-29

Applicant: Intel IP Corporation

Inventor： Bernd Waidhas ,  Stephan Stoeckl ,  Andreas Wolter ,  Reinhard Mahnkopf ,  Georg Seidemann ,  Thomas Wagner ,  Laurent Millou

IPC: H01L23/06 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L23/053

Abstract: A bent-bridge semiconductive apparatus includes a silicon bridge that is integral to a semiconductive device and the silicon bridge is deflected out of planarity. The silicon bridge may couple two semiconductive devices, all of which are from an integral processed die.

公开(公告)号：US20190341371A1

公开(公告)日：2019-11-07

申请号：US16515979

申请日：2019-07-18

Applicant: Intel IP Corporation

Inventor： Bernd Waidhas ,  Georg Seidemann ,  Andreas Augustin ,  Laurent Millou ,  Andreas Wolter ,  Reinhard Mahnkopf ,  Stephan Stoeckl ,  Thomas Wagner

IPC: H01L25/065 ,  H01L25/10 ,  H01L21/48 ,  H01L23/48 ,  H01L25/00

Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.

公开(公告)号：US11018114B2

公开(公告)日：2021-05-25

申请号：US16515979

申请日：2019-07-18

Applicant: Intel IP Corporation

Inventor： Bernd Waidhas ,  Georg Seidemann ,  Andreas Augustin ,  Laurent Millou ,  Andreas Wolter ,  Reinhard Mahnkopf ,  Stephan Stoeckl ,  Thomas Wagner

IPC: H01L25/10 ,  H01L25/065 ,  H01L21/48 ,  H01L23/48 ,  H01L25/00 ,  H01L23/427 ,  G06F15/76

Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.