公开(公告)号：US20200066692A1

公开(公告)日：2020-02-27

申请号：US16344633

申请日：2016-12-14

Applicant: INTEL IP CORPORATION

Inventor： Andreas WOLTER ,  Bernd WAIDHAS ,  Georg SEIDEMANN ,  Klaus REINGRUBER ,  Thomas WAGNER

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48

Abstract: Package devices (systems and methods for their manufacture) may have an integrated circuit (IC) chip mounted on a top surface of a package substrate of and IC package, and embedded in a mold compound formed onto the top surface. They may also have conductive elements mounted on the top surface of the package substrate, embedded in the mold compound, horizontally disposed at a first vertical sidewall of the package device, and having vertical contact pads exposed at the first vertical sidewall. Conductor material traces of the IC package may electrically couple contacts of the chip to the conductive elements. Traces of the IC package may also electrically couple contacts of the chip to bottom surface contacts of the IC package. The vertical contact pads provide a shorter signal path to another device having vertically mounted surface contacts or opposing contact pads, thus improving signaling to the other device.

公开(公告)号：US20200185490A1

公开(公告)日：2020-06-11

申请号：US16617548

申请日：2017-06-30

Applicant: INTEL IP CORPORATION

Inventor： Georg Seidemann ,  Bernd WAIDHAS ,  Thomas WAGNER ,  Andreas WOLTER ,  Andreas AUGUSTIN

IPC: H01L49/02 ,  H01L23/64 ,  H01L23/00 ,  H01L21/02 ,  H01L21/56 ,  H01F17/04

Abstract: The present disclosure is directed to systems and methods for fabricating a semiconductor inductor that includes a coil deposited on a stop layer that is deposited on a sacrificial substrate. The semiconductor inductor may be fabricated on a silicon wafer and singulated. The sacrificial substrate beneficially provides structural support for the singulated semiconductor inductor. The singulated semiconductor inductor advantageously requires minimal active die surface area. The removal of the sacrificial substrate after coupling to the active die beneficially reduces the overall thickness (or height) of the semiconductor package, providing a decided advantage in low profile, portable, electronic devices.

公开(公告)号：US20220122756A1

公开(公告)日：2022-04-21

申请号：US17566529

申请日：2021-12-30

Applicant: Intel IP Corporation

Inventor： Andreas WOLTER ,  Thorsten MEYER ,  Gerhard KNOBLINGER

IPC: H01F17/00 ,  H01F41/04 ,  H01L23/64 ,  H01L23/522 ,  H01L23/00

Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.

公开(公告)号：US20200381161A1

公开(公告)日：2020-12-03

申请号：US16993152

申请日：2020-08-13

Applicant: Intel IP Corporation

Inventor： Andreas WOLTER ,  Thorsten MEYER ,  Gerhard KNOBLINGER

IPC: H01F17/00 ,  H01F41/04 ,  H01L23/64 ,  H01L23/522 ,  H01L23/00

Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.

公开(公告)号：US20200328182A1

公开(公告)日：2020-10-15

申请号：US16915282

申请日：2020-06-29

Applicant: Intel IP Corporation

Inventor： Bernd WAIDHAS ,  Georg SEIDEMANN ,  Andreas WOLTER ,  Thomas WAGNER ,  Stephan Stoeckl ,  Laurent MILLOU

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L21/683

Abstract: An embedded-bridge substrate connector apparatus includes a patterned reference layer to which a first module and a subsequent module are aligned and the two modules are mated at the patterned reference layer. At least one module includes a silicon bridge connector that bridges to two devices, through the patterned reference layer, to the mated module.

公开(公告)号：US20180331053A1

公开(公告)日：2018-11-15

申请号：US15776474

申请日：2015-12-21

Applicant: Intel IP Corporation

Inventor： Christian GEISSLER ,  Sven ALBERS ,  Georg SEIDEMANN ,  Andreas WOLTER ,  Klaus REINGRUBER ,  Thomas WAGNER ,  Marc DITTES

IPC: H01L23/00

Abstract: An electrical device includes a redistribution layer structure, an inter-diffusing material contact structure and a vertical electrically conductive structure located between the redistribution layer structure and the inter-diffusing material contact structure. The vertical electrically conductive structure includes a diffusion barrier structure located adjacently to the inter-diffusing material contact structure. Further, the diffusion barrier structure and the redistribution layer structure comprise different lateral dimensions.

公开(公告)号：US20190393191A1

公开(公告)日：2019-12-26

申请号：US16464213

申请日：2016-12-27

Applicant: Intel IP Corporation

Inventor： Klaus REINGRUBER ,  Georg SEIDEMANN ,  Andreas WOLTER ,  Bernd WAIDHAS ,  Thomas WAGNER

IPC: H01L25/065 ,  H01L23/48 ,  H01L25/00 ,  H01L21/768

Abstract: Embodiments may include an IC having an active substrate containing devices, and a bulk substrate, separated by an oxide layer or an etching stop layer. The IC may be partially thinned from a backside of the bulk substrate to create a cavity, while maintaining the dicing streets and/or the edges of the bulk substrate without being thinned. The cavity may be surrounded by a first edge and a second edge of the bulk substrate. An additional IC may be placed within the cavity of the bulk substrate to form a stacking IC with a reduced height. The ICs of the stacking IC may be electronically coupled using TSVs embedded within the active substrate of the ICs. Other embodiments may be described and/or claimed.

公开(公告)号：US20190214369A1

公开(公告)日：2019-07-11

申请号：US16325970

申请日：2016-09-28

Applicant: Intel IP Corporation

Inventor： Georg SEIDEMANN ,  Thomas WAGNER ,  Klaus REINGRUBER ,  Bernd WAIDHAS ,  Andreas WOLTER

IPC: H01L25/065 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/00 ,  H01L23/31 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L29/0657 ,  H01L2224/05 ,  H01L2224/13025 ,  H01L2224/16227 ,  H01L2224/24051 ,  H01L2224/24147 ,  H01L2224/244 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48148 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2924/10158 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2924/00

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing reduced height semiconductor packages for mobile electronics. For instance, there is disclosed in accordance with one embodiment a stacked die package having therein a bottom functional silicon die; a recess formed within the bottom functional silicon die by a thinning etch partially reducing a vertical height of the bottom functional silicon die at the recess; and a top component positioned at least partially within the recess formed within the bottom functional silicon die. Other related embodiments are disclosed.

公开(公告)号：US20190206833A1

公开(公告)日：2019-07-04

申请号：US15772730

申请日：2015-12-23

Applicant: Intel IP Corporation

Inventor： Thorsten MEYER ,  Klaus REINGRUBER ,  Georg SEIDEMANN ,  Andreas WOLTER ,  Christian GEISSLER ,  Sven ALBERS

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L25/0652 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/00 ,  H01L24/12 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L25/065 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/06548 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19106

Abstract: Embodiments of the invention include an eWLB or ePLB based PoP device and methods of forming such devices. According to an embodiment, such a device may include a die embedded within a mold layer. A substrate may be directly contacting a surface of the mold layer. Additionally, embodiments of the invention may include a through mold via formed through the mold layer that is electrically coupled to a contact formed on a surface of the substrate that is contacting the mold layer. In order to form such a device, embodiments may include dispensing a molding material over a die positioned on a mold carrier. Thereafter, a substrate may be pressed into the molding material. After curing the molding material, a mold layer may be formed that encases the die and is adhered to the substrate.

公开(公告)号：US20180331070A1

公开(公告)日：2018-11-15

申请号：US15774906

申请日：2015-12-26

Applicant: Intel IP Corporation

Inventor： Georg SEIDEMANN ,  Klaus REINGRUBER ,  Christian GEISSLER ,  Sven ALBERS ,  Andreas WOLTER ,  Marc DITTES ,  Richard PATTEN

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/2518 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/92224 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81

Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.