公开(公告)号：US20220122756A1

公开(公告)日：2022-04-21

申请号：US17566529

申请日：2021-12-30

Applicant: Intel IP Corporation

Inventor： Andreas WOLTER ,  Thorsten MEYER ,  Gerhard KNOBLINGER

IPC: H01F17/00 ,  H01F41/04 ,  H01L23/64 ,  H01L23/522 ,  H01L23/00

Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.

公开(公告)号：US20200381161A1

公开(公告)日：2020-12-03

申请号：US16993152

申请日：2020-08-13

Applicant: Intel IP Corporation

Inventor： Andreas WOLTER ,  Thorsten MEYER ,  Gerhard KNOBLINGER

IPC: H01F17/00 ,  H01F41/04 ,  H01L23/64 ,  H01L23/522 ,  H01L23/00

Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.

公开(公告)号：US20190206833A1

公开(公告)日：2019-07-04

申请号：US15772730

申请日：2015-12-23

Applicant: Intel IP Corporation

Inventor： Thorsten MEYER ,  Klaus REINGRUBER ,  Georg SEIDEMANN ,  Andreas WOLTER ,  Christian GEISSLER ,  Sven ALBERS

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L25/0652 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/00 ,  H01L24/12 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L25/065 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/06548 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19106

Abstract: Embodiments of the invention include an eWLB or ePLB based PoP device and methods of forming such devices. According to an embodiment, such a device may include a die embedded within a mold layer. A substrate may be directly contacting a surface of the mold layer. Additionally, embodiments of the invention may include a through mold via formed through the mold layer that is electrically coupled to a contact formed on a surface of the substrate that is contacting the mold layer. In order to form such a device, embodiments may include dispensing a molding material over a die positioned on a mold carrier. Thereafter, a substrate may be pressed into the molding material. After curing the molding material, a mold layer may be formed that encases the die and is adhered to the substrate.