公开(公告)号：US20190043800A1

公开(公告)日：2019-02-07

申请号：US16152221

申请日：2018-10-04

Applicant: Intel IP Corporation

Inventor： Klaus Jürgen REINGRUBER ,  Sven ALBERS ,  Christian Georg GEISSLER ,  Georg SEIDEMANN ,  Bernd WAIDHAS ,  Thomas WAGNER ,  Marc DITTES

IPC: H01L23/528 ,  H05K1/11 ,  H01L23/00 ,  H01L23/498 ,  C25D5/10 ,  C25D7/12 ,  C25D5/02 ,  H01L23/522 ,  C25D5/48 ,  C25D5/54 ,  H05K1/02

Abstract: Semiconductor packages having variable redistribution layer thicknesses are described. In an example, a semiconductor package includes a redistribution layer on a dielectric layer, and the redistribution layer includes first conductive traces having a first thickness and second conductive traces having a second thickness. The first thickness may be different than the second thickness, e.g., the first thickness may be less than the second thickness.

公开(公告)号：US20180358317A1

公开(公告)日：2018-12-13

申请号：US15776051

申请日：2015-12-23

Applicant: Intel IP Corporation

Inventor： Sven ALBERS ,  Klaus REINGRUBER ,  Georg SEIDEMANN ,  Christian GEISSLER ,  Richard PATTEN

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/36 ,  H01L23/552 ,  H01L23/433 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48

Abstract: An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.

公开(公告)号：US20180331053A1

公开(公告)日：2018-11-15

申请号：US15776474

申请日：2015-12-21

Applicant: Intel IP Corporation

Inventor： Christian GEISSLER ,  Sven ALBERS ,  Georg SEIDEMANN ,  Andreas WOLTER ,  Klaus REINGRUBER ,  Thomas WAGNER ,  Marc DITTES

IPC: H01L23/00

Abstract: An electrical device includes a redistribution layer structure, an inter-diffusing material contact structure and a vertical electrically conductive structure located between the redistribution layer structure and the inter-diffusing material contact structure. The vertical electrically conductive structure includes a diffusion barrier structure located adjacently to the inter-diffusing material contact structure. Further, the diffusion barrier structure and the redistribution layer structure comprise different lateral dimensions.

公开(公告)号：US20200273832A1

公开(公告)日：2020-08-27

申请号：US16871325

申请日：2020-05-11

Applicant: Intel IP Corporation

Inventor： Sven ALBERS ,  Klaus REINGRUBER ,  Georg SEIDEMANN ,  Christian GEISSLER ,  Richard PATTEN

IPC: H01L23/00 ,  H01L23/433 ,  H01L21/56 ,  H01L23/552 ,  H01L21/48 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498

Abstract: An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.

公开(公告)号：US20200176436A1

公开(公告)日：2020-06-04

申请号：US15776378

申请日：2015-12-23

Applicant: Intel IP Corporation

Inventor： Sven ALBERS ,  Klaus REINGRUBER ,  Richard PATTEN ,  Georg SEIDEMANN ,  Christian GEISSLER

IPC: H01L25/00 ,  H01L25/065

Abstract: An apparatus is described that includes a semiconductor die package. The semiconductor die package includes a semiconductor die package substrate having a top side and a bottom side. The semiconductor die package includes I/O balls on the bottom side of the semiconductor die package substrate. The I/O balls are to mount to a planar board. The semiconductor die package includes a first semiconductor die mounted on the bottom side of the semiconductor die package substrate. The first semiconductor die is vertically located between the bottom side of the semiconductor die package substrate and a second semiconductor die that is a part of the semiconductor die package.

公开(公告)号：US20190206833A1

公开(公告)日：2019-07-04

申请号：US15772730

申请日：2015-12-23

Applicant: Intel IP Corporation

Inventor： Thorsten MEYER ,  Klaus REINGRUBER ,  Georg SEIDEMANN ,  Andreas WOLTER ,  Christian GEISSLER ,  Sven ALBERS

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L25/0652 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/00 ,  H01L24/12 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L25/065 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/06548 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19106

Abstract: Embodiments of the invention include an eWLB or ePLB based PoP device and methods of forming such devices. According to an embodiment, such a device may include a die embedded within a mold layer. A substrate may be directly contacting a surface of the mold layer. Additionally, embodiments of the invention may include a through mold via formed through the mold layer that is electrically coupled to a contact formed on a surface of the substrate that is contacting the mold layer. In order to form such a device, embodiments may include dispensing a molding material over a die positioned on a mold carrier. Thereafter, a substrate may be pressed into the molding material. After curing the molding material, a mold layer may be formed that encases the die and is adhered to the substrate.

公开(公告)号：US20180331070A1

公开(公告)日：2018-11-15

申请号：US15774906

申请日：2015-12-26

Applicant: Intel IP Corporation

Inventor： Georg SEIDEMANN ,  Klaus REINGRUBER ,  Christian GEISSLER ,  Sven ALBERS ,  Andreas WOLTER ,  Marc DITTES ,  Richard PATTEN

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/2518 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/92224 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81

Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.