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公开(公告)号：US09729963B2
公开(公告)日：2017-08-08
申请号：US14074587
申请日：2013-11-07
Applicant: InvenSense, Inc.
Inventor： Baris Cagdaser , Omid Oliaei , Behrad Aria
CPC classification number: H04R3/00 , H04R1/08 , H04R19/005 , H04R2201/003
Abstract: A programmable acoustic sensor is disclosed. The programmable acoustic sensor includes a MEMS transducer and a programmable circuitry coupled to the MEMS transducer. The programmable circuitry includes a power pin and a ground pin. The programmable acoustic sensor also includes a communication channel enabling data exchange between the programmable circuitry and a host system. One of the power pin and the ground pin can be utilized for data exchange.
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2.发明授权Multiple, per sensor configurable FIFOs in a single static random access memory (SRAM) structure 有权多个，每个传感器可配置的FIFO在单个静态随机存取存储器（SRAM）结构中公开(公告)号：US09235377B2
公开(公告)日：2016-01-12
申请号：US13796997
申请日：2013-03-12
Applicant: Invensense, Inc.
Inventor： Vinod Bhat , Behrad Aria
CPC classification number: G06F5/10 , G06F5/065 , G06F12/0223 , G06F12/0646 , G06F2205/063
Abstract: A device includes one or more sensors, one or more processors, one or more sensors, and a memory. The memory has a first portion, a second portion, and a third portion. The first portion is allocated to storing instructions for execution by the one or more processors. The second portion is allocated to storing data generated by the one or more processor, and the third portion is allocated to storing data from the one or more sensors. The third portion being a first-in-first-out (FIFO) having one or more FIFO portions, The device further includes a control logic operable to allocate the first, second and third portions of the memory, wherein each of one or more FIFO portions is allocated to each of the one or more sensors. The size each of the FIFO portions depends on the bandwidth of the sensors and the number of sensors.
Abstract translation: 设备包括一个或多个传感器，一个或多个处理器，一个或多个传感器和存储器。 存储器具有第一部分，第二部分和第三部分。 第一部分被分配用于存储由一个或多个处理器执行的指令。 分配第二部分以存储由一个或多个处理器生成的数据，并且第三部分被分配用于存储来自一个或多个传感器的数据。 第三部分是具有一个或多个FIFO部分的先进先出（FIFO）。该设备还包括可操作以分配存储器的第一，第二和第三部分的控制逻辑，其中一个或多个FIFO中的每一个 部分被分配给一个或多个传感器中的每一个。 每个FIFO部分的大小取决于传感器的带宽和传感器的数量。
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3.发明授权公开(公告)号：US09086730B2
公开(公告)日：2015-07-21
申请号：US13673882
申请日：2012-11-09
Applicant: InvenSense, Inc.
Inventor： Behrad Aria , David Sachs , Joseph Seeger
CPC classification number: G06F3/017 , G06F3/03 , G06F3/0412
Abstract: Selectable communication interface configurations for motion sensing devices. In one aspect, a module for a motion sensing device includes a motion processor connected to a device component and a first motion sensor, and a multiplexer having first and second positions. Only one of the multiplexer positions is selectable at a time, where the first position selectively couples the first motion sensor and the device component using a first bus, and the second position selectively couples the first motion sensor and the motion processor using a second bus, wherein communication of information over the second bus does not influence a communication bandwidth of the first bus.
Abstract translation: 运动感应装置可选择的通讯接口配置。 一方面，用于运动感测装置的模块包括连接到装置部件和第一运动传感器的运动处理器以及具有第一和第二位置的多路复用器。 一次只能选择一个多路复用器位置，其中第一位置使用第一总线选择性地耦合第一运动传感器和设备部件，并且第二位置使用第二总线选择性地耦合第一运动传感器和运动处理器， 其中通过第二总线的信息通信不影响第一总线的通信带宽。
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4.发明申请MULTIPLE, PER SENSOR CONFIGURABLE FIFOS IN A SINGLE STATIC RANDOM ACCESS MEMORY (SRAM) STRUCTURE 有权单个静态随机访问存储器（SRAM）结构中的多个传感器配置FIFOS公开(公告)号：US20140281341A1
公开(公告)日：2014-09-18
申请号：US13796997
申请日：2013-03-12
Applicant: INVENSENSE, INC.
Inventor： Vinod Bhat , Behrad Aria
IPC: G06F5/14
CPC classification number: G06F5/10 , G06F5/065 , G06F12/0223 , G06F12/0646 , G06F2205/063
Abstract: A device includes one or more sensors, one or more processors, one or more sensors, and a memory. The memory has a first portion, a second portion, and a third portion. The first portion is allocated to storing instructions for execution by the one or more processors. The second portion is allocated to storing data generated by the one or more processor, and the third portion is allocated to storing data from the one or more sensors. The third portion being a first-in-first-out (FIFO) having one or more FIFO portions, The device further includes a control logic operable to allocate the first, second and third portions of the memory, wherein each of one or more FIFO portions is allocated to each of the one or more sensors. The size each of the FIFO portions depends on the bandwidth of the sensors and the number of sensors.
Abstract translation: 设备包括一个或多个传感器，一个或多个处理器，一个或多个传感器和存储器。 存储器具有第一部分，第二部分和第三部分。 第一部分被分配用于存储由一个或多个处理器执行的指令。 分配第二部分以存储由一个或多个处理器生成的数据，并且第三部分被分配用于存储来自一个或多个传感器的数据。 第三部分是具有一个或多个FIFO部分的先进先出（FIFO）。该设备还包括可操作以分配存储器的第一，第二和第三部分的控制逻辑，其中一个或多个FIFO中的每一个 部分被分配给一个或多个传感器中的每一个。 每个FIFO部分的大小取决于传感器的带宽和传感器的数量。
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