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    ACTUATOR LAYER PATTERNING WITH TOPOGRAPHY
    1.
    发明申请
    ACTUATOR LAYER PATTERNING WITH TOPOGRAPHY 审中-公开

    公开(公告)号：WO2022076079A1

    公开(公告)日：2022-04-14

    申请号：PCT/US2021/045428

    申请日：2021-08-10

    Applicant: INVENSENSE, INC.

    Inventor： LEE, Daesung ,  CUTHBERTSON, Alan

    IPC: B81B7/00 ,  B81C1/00

    Abstract: A method including fusion bonding a handle wafer to a first side of a device wafer. The method further includes depositing a hardmask on a second side of the device wafer, wherein the second side is planar. An etch stop layer is deposited over the hardmask and an exposed portion of the second side of the device wafer. A dielectric layer is formed over the etch stop layer. A via is formed within the dielectric layer. The via is filled with conductive material. A eutectic bond layer is formed over the conductive material. Portions of the dielectric layer uncovered by the eutectic bond layer is etched to expose the etch stop layer. The exposed portions of the etch stop layer is etched. A micro-electro-mechanical system (MEMS) device pattern is etched into the device wafer.

    METHOD AND SYSTEM FOR FABRICATING A MEMS DEVICE
    2.
    发明申请
    METHOD AND SYSTEM FOR FABRICATING A MEMS DEVICE 审中-公开

    公开(公告)号：WO2023014603A1

    公开(公告)日：2023-02-09

    申请号：PCT/US2022/038850

    申请日：2022-07-29

    Applicant: INVENSENSE, INC.

    Inventor： LEE, Daesung ,  CUTHBERTSON, Alan

    IPC: B81B3/00

    Abstract: A device includes a substrate and an intermetal dielectric (IMD) layer disposed over the substrate. The device also includes a first plurality of polysilicon layers disposed over the IMD layer and over a bumpstop. The device also includes a second plurality of polysilicon layers disposed within the IMD layer. The device includes a patterned actuator layer with a first side and a second side, wherein the first side of the patterned actuator layer is lined with a polysilicon layer, and wherein the first side of the patterned actuator layer faces the bumpstop. The device further includes a standoff formed over the IMD layer, a via through the standoff making electrical contact with the polysilicon layer of the actuator and a portion of the second plurality of polysilicon layers and a bond material disposed on the second side of the patterned actuator layer.

    ACTUATOR LAYER PATTERNING WITH POLYSILICON AND ETCH STOP LAYER
    3.
    发明申请
    ACTUATOR LAYER PATTERNING WITH POLYSILICON AND ETCH STOP LAYER 审中-公开

    公开(公告)号：WO2022250762A1

    公开(公告)日：2022-12-01

    申请号：PCT/US2022/020333

    申请日：2022-03-15

    Applicant: INVENSENSE, INC.

    Inventor： UDDIN, Ashfaque ,  LEE, Daesung ,  CUTHBERTSON, Alan

    IPC: B81C1/00

    Abstract: A method includes forming an etch stop layer over a first side of a device wafer. The method also includes forming a polysilicon layer over the etch stop layer. A handle wafer is fusion bonded to the first side of the device wafer. A eutectic bond layer is formed on a second side of the device wafer. A micro-electro-mechanical system (MEMS) features are etched into the second side of the device wafer to expose the etch stop layer. The exposed etch stop layer is removed to expose the polysilicon layer. The exposed polysilicon layer is removed to expose a cavity formed between the handle wafer and the device wafer.

    MEMS TAB REMOVAL PROCESS
    4.
    发明申请
    MEMS TAB REMOVAL PROCESS 审中-公开

    公开(公告)号：WO2022132574A1

    公开(公告)日：2022-06-23

    申请号：PCT/US2021/062754

    申请日：2021-12-10

    Applicant: INVENSENSE, INC.

    Inventor： LEE, Daesung ,  CUTHBERTSON, Alan

    IPC: B81C1/00

    Abstract: A method includes tab dicing a region of a tab region disposed between a first die and a second die. The tab region structurally connects the first die to the second die each including a MEMS device eutecticly bonded to a CMOS device. The tab region includes a handle wafer layer disposed over a fusion bond oxide layer that is disposed on an ACT layer. The tab region is positioned above a CMOS tab region that with the first and second die form a cavity therein. The tab dicing cuts through the handle wafer layer and leaves a portion of the fusion bond oxide layer underneath the handle wafer layer to form an oxide tether within the tab region. The oxide tether maintains the tab region in place and above the CMOS tab region. Subsequent to the tab dicing the first region, the tab region is removed.

    METHOD AND SYSTEM FOR FABRICATING A MEMS DEVICE CAP
    6.
    发明申请
    METHOD AND SYSTEM FOR FABRICATING A MEMS DEVICE CAP 审中-公开

    公开(公告)号：WO2023014606A1

    公开(公告)日：2023-02-09

    申请号：PCT/US2022/038861

    申请日：2022-07-29

    Applicant: INVENSENSE, INC.

    Inventor： LEE, Daesung ,  CUTHBERTSON, Alan

    IPC: B81B7/02 ,  B81B7/00 ,  B81C1/00

    Abstract: A device includes a substrate comprising a first standoff, a second standoff, a third standoff, a first cavity, a second cavity, and a bonding material covering a portion of the first, the second, and the third standoff. The first cavity is positioned between the first and the second standoffs, and the second cavity is positioned between the second and the third standoffs. The first cavity comprises a first cavity region and a second cavity region separated by a portion of the substrate extruding thereto, and wherein a depth associated with the first cavity region is greater than a depth associated with the second cavity. A surface of the first cavity is covered with a getter material.

    METHOD AND SYSTEM FOR FABRICATING A MEMS DEVICE
    7.
    发明申请
    METHOD AND SYSTEM FOR FABRICATING A MEMS DEVICE 审中-公开

    公开(公告)号：WO2023014599A1

    公开(公告)日：2023-02-09

    申请号：PCT/US2022/038835

    申请日：2022-07-29

    Applicant: INVENSENSE, INC.

    Inventor： LEE, Daesung ,  CUTHBERTSON, Alan

    IPC: B81B3/00

    Abstract: A method includes forming a bumpstop from a first intermetal dielectric (IMD) layer and forming a via within the first IMD, wherein the first IMD is disposed over a first polysilicon layer, and wherein the first polysilicon layer is disposed over another IMD layer that is disposed over a substrate. The method further includes depositing a second polysilicon layer over the bumpstop and further over the via to connect to the first polysilicon layer. A standoff is formed over a first portion of the second polysilicon layer, and wherein a second portion of the second polysilicon layer is exposed. The method includes depositing a bond layer over the standoff.

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