公开(公告)号：US20070018304A1

公开(公告)日：2007-01-25

申请号：US11470541

申请日：2006-09-06

Applicant: John Tellkamp ,  Akira Matsunami

Inventor： John Tellkamp ,  Akira Matsunami

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: B23K35/262 ,  B23K35/286 ,  B23K35/302 ,  B23K35/3033 ,  B23K35/325 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/81024 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83851 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01083

Abstract: An integrated circuit chip which has a plurality of pads and non-reflowable contact members to be connected by reflow attachment to external parts. Each of these contact members has a height-to-diameter ratio and uniform diameter favorable for absorbing strain under thermo-mechanical stress. The members have a solderable surface on each end and a layer of reflowable material on each end. Each member is solder-attached at one end to a chip contact pad, while the other end of each member is operable for reflow attachment to external parts.

Abstract translation: 一种集成电路芯片，其具有多个焊盘和不可回流接触部件，以通过回流附接到外部部件来连接。 这些接触构件中的每一个具有高度 - 直径比和均匀的直径，其有利于在热机械应力下吸收应变。 这些构件在每一端具有可焊接表面，并且在每一端具有一层可回流材料。 每个构件的一端被焊接附接到芯片接触垫，而每个构件的另一端可操作用于回流附接到外部部件。

公开(公告)号：US20060019418A1

公开(公告)日：2006-01-26

申请号：US10896808

申请日：2004-07-22

Applicant: John Tellkamp

Inventor： John Tellkamp

IPC: H01L21/66

CPC classification number: H01L24/83 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/0204 ,  H05K1/0206 ,  H05K3/0005 ,  H05K3/341 ,  H05K2201/0367 ,  H05K2201/09745 ,  H05K2201/10689 ,  H05K2201/10969 ,  H05K2203/162 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of reducing a likelihood that a die pad will be delaminated from a die in an integrated circuit die package for a structure design during an attachment of a heat sink member to the die pad using solder, is provided. A sample structure of the structure design is evaluated to determine whether a volume of last solidification for the solder is centrally located with respect to the die pad and is located at or near an interface of the solder and the die pad. If the last solidification volume is centrally located and is located at or near the interface of the solder and the die pad, and if the die pad is delaminated from the die, the structure design is modified so that less metal of the heat sink member is centrally located than before the modifying.

Abstract translation: 提供了一种降低在使用焊料将散热构件附接到裸片焊盘期间用于结构设计的集成电路管芯封装中的管芯焊盘从管芯剥离的可能性的方法。 评估结构设计的样品结构以确定焊料的最后凝固体积是否相对于芯片焊盘位于中心位置，并且位于焊料和管芯焊盘的界面处或附近。 如果最后一个凝固体位于中心位置并且位于焊料和管芯焊盘的界面处或附近，并且如果管芯焊盘从模具分层，则结构设计被修改，使得散热构件的金属少于 位于中心位置比修改前。

公开(公告)号：US20090091007A1

公开(公告)日：2009-04-09

申请号：US11867821

申请日：2007-10-05

Applicant: John Tellkamp

Inventor： John Tellkamp

IPC: H01L23/495 ,  H01L21/60

CPC classification number: H01L23/49548 ,  H01L21/4828 ,  H01L21/4842 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/3426 ,  H05K2201/10689 ,  H05K2201/10848 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012

Abstract: A packaged surface-mount semiconductor device has the outer, un-encapsulated lead segments structured in five adjoining portions: The first portion protrudes from the encapsulation about horizontally; the second portion forms a convex bend downwardly; the third portion is approximately straight downwardly; the fourth portion forms a concave bend upwardly; and the fifth portion is straight horizontally. Each segment has across the width a first groove in the third portion, either on the bottom surface or on the top surface. Preferably, the groove is about 2 leadframe thicknesses vertically over the bottom surface of the fifth lead portion. When stamped, the groove may have an angular outline about 5 and 50 μm deep; when etched, the groove may have an approximately semicircular outline about 50 to 125 μm deep. A second groove may be located in the second segment portion; a third groove may be located in the transition region from the third to the fourth segment portions.

Abstract translation: 封装的表面贴装半导体器件具有构造在五个相邻部分中的外部未封装引线段：第一部分围绕水平从封装突出; 第二部分向下形成凸起的弯曲部分; 第三部分大致直线向下; 第四部分向上形成凹弯; 第五部分是水平的。 每个段在宽度上具有第三部分中的第一凹槽，无论是在底表面上还是在顶表面上。 优选地，凹槽在垂直于第五引线部分的底表面上的约2个引线框厚度。 当冲压时，凹槽可以具有大约5和50毫米深的角轮廓; 当蚀刻时，凹槽可以具有约50至125μm深的约半圆形轮廓。 第二槽可以位于第二段部分中; 第三凹槽可以位于从第三分段部分到第四分段部分的过渡区域中。

公开(公告)号：US20070092999A1

公开(公告)日：2007-04-26

申请号：US11614167

申请日：2006-12-21

Applicant: John Tellkamp

Inventor： John Tellkamp

IPC: H01L21/00

CPC classification number: H01L24/83 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/0204 ,  H05K1/0206 ,  H05K3/0005 ,  H05K3/341 ,  H05K2201/0367 ,  H05K2201/09745 ,  H05K2201/10689 ,  H05K2201/10969 ,  H05K2203/162 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of reducing a likelihood that a die pad will be delaminated from a die in an integrated circuit die package for a structure design during an attachment of a heat sink member to the die pad using solder, is provided. A sample structure of the structure design is evaluated to determine whether a volume of last solidification for the solder is centrally located with respect to the die pad and is located at or near an interface of the solder and the die pad. If the last solidification volume is centrally located and is located at or near the interface of the solder and the die pad, and if the die pad is delaminated from the die, the structure design is modified so that less metal of the heat sink member is centrally located than before the modifying.

Abstract translation: 提供了一种降低在使用焊料将散热构件附接到裸片焊盘期间用于结构设计的集成电路管芯封装中的管芯焊盘从管芯剥离的可能性的方法。 评估结构设计的样品结构以确定焊料的最后凝固体积是否相对于芯片焊盘位于中心位置，并且位于焊料和管芯焊盘的界面处或附近。 如果最后一个凝固体位于中心位置并且位于焊料和管芯焊盘的界面处或附近，并且如果管芯焊盘从模具分层，则结构设计被修改，使得散热构件的金属少于 位于中心位置比修改前。

公开(公告)号：US20060156080A1

公开(公告)日：2006-07-13

申请号：US11009290

申请日：2004-12-10

Applicant: John Tellkamp ,  Sandra Horton

Inventor： John Tellkamp ,  Sandra Horton

IPC: G11B20/20 ,  G06K5/04 ,  G11B5/00

CPC classification number: G01R31/2896 ,  G01R31/2874 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: According to one embodiment of the present invention, a method for detecting a defect in an integrated circuit using an optimized power pulse includes applying a first pulse of power to a first integrated circuit for an optimized pulse duration. The optimized pulse duration is determined as a function of a difference in temperature between a second, defective integrated circuit and a third, non-defective integrated circuit. The temperature of the first integrated circuit is measured after the first pulse of power is applied to the first integrated circuit for the optimized pulse duration, and a determination is made as to whether the first integrated circuit is defective based on the temperature of the first integrated circuit.

Abstract translation: 根据本发明的一个实施例，使用优化的功率脉冲来检测集成电路中的缺陷的方法包括将第一脉冲功率施加到第一集成电路以获得优化的脉冲持续时间。 优化的脉冲持续时间被确定为第二故障集成电路和第三无缺陷集成电路之间的温度差的函数。 在对第一集成电路施加第一脉冲以优化的脉冲持续时间之后，测量第一集成电路的温度，并且基于第一集成电路的温度确定第一集成电路是否有缺陷 电路。

公开(公告)号：US07821111B2

公开(公告)日：2010-10-26

申请号：US11867821

申请日：2007-10-05

Applicant: John Tellkamp

Inventor： John Tellkamp

IPC: H01L23/495 ,  H01L23/28

CPC classification number: H01L23/49548 ,  H01L21/4828 ,  H01L21/4842 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/3426 ,  H05K2201/10689 ,  H05K2201/10848 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012

Abstract: A packaged surface-mount semiconductor device has the outer, un-encapsulated lead segments structured in five adjoining portions: The first portion protrudes from the encapsulation about horizontally; the second portion forms a convex bend downwardly; the third portion is approximately straight downwardly; the fourth portion forms a concave bend upwardly; and the fifth portion is straight horizontally. Each segment has across the width a first groove in the third portion, either on the bottom surface or on the top surface. Preferably, the groove is about 2 leadframe thicknesses vertically over the bottom surface of the fifth lead portion. When stamped, the groove may have an angular outline about 5 and 50 μm deep; when etched, the groove may have an approximately semicircular outline about 50 to 125 μm deep. A second groove may be located in the second segment portion; a third groove may be located in the transition region from the third to the fourth segment portions.

Abstract translation: 封装的表面贴装半导体器件具有构造在五个相邻部分中的外部未封装引线段：第一部分围绕水平从封装突出; 第二部分向下形成凸起的弯曲部分; 第三部分大致直线向下; 第四部分向上形成凹弯; 第五部分是水平的。 每个段在宽度上具有第三部分中的第一凹槽，无论是在底表面上还是在顶表面上。 优选地，凹槽在垂直于第五引线部分的底表面上的约2个引线框厚度。 当冲压时，凹槽可以具有约5和50μm深的角轮廓; 当蚀刻时，凹槽可以具有约50至125μm深的近似半圆形轮廓。 第二槽可以位于第二段部分中; 第三凹槽可以位于从第三分段部分到第四分段部分的过渡区域中。

公开(公告)号：US20080014757A1

公开(公告)日：2008-01-17

申请号：US11774914

申请日：2007-07-09

Applicant: John Tellkamp

Inventor： John Tellkamp

IPC: H01L21/00

CPC classification number: H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/85464 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  Y10T428/12868 ,  Y10T428/12875 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device has a leadframe with a structure made of a base metal (105), wherein the structure consists of a chip mount pad (302) and a plurality of lead segments (303). Covering the base metal are, consecutively, a continuous nickel layer (201) on the base metal, a layer of palladium on the nickel, wherein the palladium layer (203) on the chip side of the structure is thicker than the palladium layer (202) opposite the chip, and a gold layer (204) on the palladium layer (202) opposite the chip. A semiconductor chip (310) is attached to the chip mount pad and conductive connections (312) span from the chip to the lead segments. Polymeric encapsulation compound (320) covers the chip, the connections, and portions of the lead segments, but leaves other segment portions available for solder reflow attachment to external parts.

Abstract translation: 半导体器件具有由基底金属（105）制成的结构的引线框架，其中该结构由芯片安装焊盘（302）和多个引线段（303）组成。 在基体金属上连续地覆盖基体金属的连续的镍层（201），镍上的钯层，其中结构的芯片侧的钯层（203）比钯层（202 ）和与芯片相对的钯层（202）上的金层（204）。 半导体芯片（310）附接到芯片安装焊盘，导电连接（312）跨越芯片到引线段。 聚合物封装化合物（320）覆盖芯片，连接部分和引线段的部分，但留下其他段部分可用于焊接回流附着到外部部件。

公开(公告)号：US20070120233A1

公开(公告)日：2007-05-31

申请号：US11290111

申请日：2005-11-30

Applicant: John Tellkamp

Inventor： John Tellkamp

IPC: H01L23/495

CPC classification number: H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/85464 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  Y10T428/12868 ,  Y10T428/12875 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device has a leadframe with a structure made of a base metal (105), wherein the structure consists of a chip mount pad (302) and a plurality of lead segments (303). Covering the base metal are, consecutively, a continuous nickel layer (201) on the base metal, a layer of palladium on the nickel, wherein the palladium layer (203) on the chip side of the structure is thicker than the palladium layer (202) opposite the chip, and a gold layer (204) on the palladium layer (202) opposite the chip. A semiconductor chip (310) is attached to the chip mount pad and conductive connections (312) span from the chip to the lead segments. Polymeric encapsulation compound (320) covers the chip, the connections, and portions of the lead segments, but leaves other segment portions available for solder reflow attachment to external parts.

Abstract translation: 半导体器件具有由基底金属（105）制成的结构的引线框架，其中该结构由芯片安装焊盘（302）和多个引线段（303）组成。 在基体金属上连续地覆盖基体金属的连续的镍层（201），镍上的钯层，其中结构的芯片侧的钯层（203）比钯层（202 ）和与芯片相对的钯层（202）上的金层（204）。 半导体芯片（310）附接到芯片安装焊盘，导电连接（312）跨越芯片到引线段。 聚合物封装化合物（320）覆盖芯片，连接部分和引线段的部分，但留下其他段部分可用于焊接回流附着到外部部件。