Abstract:
PROBLEM TO BE SOLVED: To provide various methods and systems for creating or performing a dynamic sampling scheme for a process during which measurement are performed on wafers.SOLUTION: The measurement is performed at all measurement spots on all of the wafers in at least one lot. An optimal sampling scheme, an enhanced sampling scheme, a reduced sampling scheme, and thresholds are determined for the dynamic sampling scheme for the process on the basis of results of the measurement. The thresholds correspond to values of the measurement at which the optimal sampling scheme, the enhanced sampling scheme, and the reduced sampling scheme for the measurement are to be used for the process.
Abstract:
PROBLEM TO BE SOLVED: To provide methods for creating or performing a dynamic sampling scheme for a measurement process on wafers, which can be used to increase accuracy of process monitoring and control.SOLUTION: A method for creating a dynamic sampling scheme for a process during which measurement is performed on wafers includes performing measurement on all of wafers in at least one lot at all measurement spots. The method also includes determining an optimal sampling scheme, an enhanced sampling scheme, a reduced sampling scheme, and thresholds for the dynamic sampling scheme for the process on the basis of results of the measurement. The thresholds correspond to measurements at which the optimal sampling scheme, the enhanced sampling scheme, and the reduced sampling scheme for the measurement are to be used for the process.
Abstract:
CONTROLLER :ios I 1110 I I PROCESSORS I MEMORY 126 122 124 (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 02 August 2018 (02.08.2018) WIP0 I PCT ill mu °million °nolo olomollm loll mum oimiE (10) International Publication Number WO 2018/140534 Al (51) International Patent Classification: GO3F 7/20 (2006.01) H01L 21/027 (2006.01) (21) International Application Number: PCT/US2018/015104 (22) International Filing Date: 24 January 2018 (24.01.2018) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 62/450,454 25 January 2017 (25.01.2017) US 15/867,485 10 January 2018 (10.01.2018) US (71) Applicant: KLA-TENCOR CORPORATION [US/US]; Legal Department, One Technology Drive, Milpitas, Cali- fornia 95035 (US). (72) Inventors: ADEL, Michael A.; 14 Yigal Alon Street, 30900 Ya'akov Zichron (IL). MANASSEN, Amnon; 10 Golda Meir, 34892 Haifa (IL). PIERSON, William; 5212 Keene Cove, Austin, Texas 78730 (US). LEVY, Ady; 1323 Glen Eyrie Avenue, San Jose, California 95125 (US). SUBRAHMANYAN, Pradeep; 22117 Wallace Dri- ve, Cupertino, California 95014 (US). YERUSHALMI, Liran; 43 Inbar, 30900 Zicron Yaacob (IL). CHOI, Dongsub; Hyundae Hometown 102-501, Seocheon-dong, Kiheung-Ku, Kyunggi Province, Yongin City 446-960 (KR). HEO, Hoyoung; 464-816,11-9, Namhansanseong- ro, 792 Beon-gil, Gwangju-si, Gyeonggi-do 31250 (KR). ALUMOT, Dror; 1 Einstein St., 7647001 Rehovot (IL). ROBINSON, John; 4000 North Hills Drive, Austin, Texas 78731 (US). (74) Agent: MCANDREWS, Kevin et al.; Kla-Tencor Corpo- ration, Legal Department, One Technology Drive, Milpitas, California 95035 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, = (54) Title: OVERLAY CONTROL WITH NON-ZERO OFFSET PREDICTION 102 112 114 148 118 116 O 00 O C 120 4111111111111111 FIG.1 B (57) : A process control system may include a controller configured to receive after-development inspection (ADI) data after a lithography step for the current layer from an ADI tool, receive after etch inspection (AEI) overlay data after an exposure step of the current layer from an AEI tool, train a non-zero offset predictor with ADI data and AEI overlay data to predict a non-zero offset from input ADI data, generate values of the control parameters of the lithography tool using ADI data and non-zero offsets generated by the non-zero offset predictor, and provide the values of the control parameters to the lithography tool for fabricating the current layer on the at least one production sample. [Continued on next page] WO 2018/140534 Al MIDEDIMODOMMERIOMMHOIREHOMMEMOIMIE CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: — with international search report (Art. 21(3))
Abstract:
A combined metrology mark, a system, and a method for calculating alignment on a semiconductor circuit are disclosed. The combined metrology mark may include a mask misregistration structure and a wafer overlay mark structure.
Abstract:
A method for automatic process control (APC) performance monitoring may include, but is not limited to: computing one or more APC performance indicators for one or more production lots of semiconductor devices; and displaying a mapping of the one or more APC performance indicators to the one or more production lots of semiconductor devices.