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    SYSTEMS, METHODS AND METRICS FOR WAFER HIGH ORDER SHAPE CHARACTERIZATION AND WAFER CLASSIFICATION USING WAFER DIMENSIONAL GEOMETRY TOOLS
    2.
    发明申请
    SYSTEMS, METHODS AND METRICS FOR WAFER HIGH ORDER SHAPE CHARACTERIZATION AND WAFER CLASSIFICATION USING WAFER DIMENSIONAL GEOMETRY TOOLS 审中-公开
    用于波形高阶形状表征的系统，方法和量度和使用波形尺寸几何工具的波浪分类

    公开(公告)号：WO2014063055A1

    公开(公告)日：2014-04-24

    申请号：PCT/US2013/065692

    申请日：2013-10-18

    Applicant: KLA-TENCOR CORPORATION

    Inventor： CHEN, Haiguang ,  SINHA, Jaydeep K. ,  KAMENSKY, Sergey ,  VEERARAGHAVAN, Sathish ,  VUKKADALA, Pradeep

    IPC: H01L21/66

    CPC classification number: G01B11/24 ,  G01B2210/56 ,  G01N21/9501 ,  G06F17/00 ,  H01L22/12

    Abstract: Systems and methods for improving results of wafer higher order shape (HOS) characterization and wafer classification are disclosed. The systems and methods in accordance with the present disclosure are based on localized shapes. A wafer map is partitioned into a plurality of measurement sites to improve the completeness of wafer shape representation. Various site based HOS metric values may be calculated for wafer characterization and/or classification purposes, and may also be utilized as control input for a downstream application. In addition, polar grid partitioning schemes are provided. Such polar grid partitioning schemes may be utilized to partition a wafer surface into measurement sites having uniform site areas while providing good wafer edge region coverage.

    Abstract translation: 公开了用于改善晶片高阶形状（HOS）表征和晶片分类的结果的系统和方法。 根据本公开的系统和方法基于局部形状。 将晶片图分割成多个测量点，以提高晶片形状表示的完整性。 可以为晶片表征和/或分类目的计算各种基于站点的HOS度量值，并且还可以用作下游应用的控制输入。 此外，还提供了极坐标分割方案。 这种极性栅格分割方案可用于将晶片表面分割成具有均匀位置区域的测量位置，同时提供良好的晶片边缘区域覆盖。

    PROCESS-INDUCED ASYMMETRY DETECTION, QUANTIFICATION, AND CONTROL USING PATTERNED WAFER GEOMETRY MEASUREMENTS
    3.
    发明申请
    PROCESS-INDUCED ASYMMETRY DETECTION, QUANTIFICATION, AND CONTROL USING PATTERNED WAFER GEOMETRY MEASUREMENTS 审中-公开
    使用图形波形几何测量的过程诱导不对称检测，量化和控制

    公开(公告)号：WO2016209625A1

    公开(公告)日：2016-12-29

    申请号：PCT/US2016/036460

    申请日：2016-06-08

    Applicant: KLA-TENCOR CORPORATION

    Inventor： VUKKADALA, Pradeep ,  SINHA, Jaydeep K ,  KIM, JH (Jong)

    IPC: H01L21/66 ,  H01L21/027

    CPC classification number: G06F17/5081 ,  G03F1/44 ,  G03F7/705 ,  G03F7/70633 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    Abstract: Systems and methods to detect, quantify, and control process-induced asymmetric signatures using patterned wafer geometry measurements are disclosed. The system may include a geometry measurement tool configured to obtain a first set of wafer geometry measurements of the wafer prior to the wafer undergoing a fabrication process and to obtain a second set of wafer geometry measurements of the wafer after the fabrication process. The system may also include a processor in communication with the geometry measurement tool. The processor may be configured to: calculate a geometry-change map based on the first set of wafer geometry measurements and the second set of wafer geometry measurements; analyze the geometry-change map to detect an asymmetric component induced to wafer geometry by the fabrication process; and estimate an asymmetric overlay error induced by the fabrication process based on the asymmetric component detected in wafer geometry.

    Abstract translation: 公开了使用图案化晶片几何测量来检测，量化和控制过程诱导的不对称签名的系统和方法。 该系统可以包括几何测量工具，其被配置成在晶片经历制造工艺之前获得晶片的第一组晶片几何测量，并且在制造工艺之后获得晶片的第二组晶片几何测量。 系统还可以包括与几何测量工具通信的处理器。 处理器可以被配置为：基于第一组晶片几何测量和第二组晶片几何测量来计算几何变化图; 分析几何变化图，以通过制造过程检测诱导到晶片几何的不对称分量; 并且基于在晶片几何中检测到的不对称分量来估计由制造工艺引起的不对称重叠误差。

    ENHANCED INSPECTION AND METROLOGY TECHNIQUES AND SYSTEMS USING BRIGHT-FIELD DIFFERENTIAL INTERFERENCE CONTRAST
    4.
    发明申请
    ENHANCED INSPECTION AND METROLOGY TECHNIQUES AND SYSTEMS USING BRIGHT-FIELD DIFFERENTIAL INTERFERENCE CONTRAST 审中-公开
    使用亮度差分干扰对比的增强检测和方法技术和系统

    公开(公告)号：WO2014164935A1

    公开(公告)日：2014-10-09

    申请号：PCT/US2014/023824

    申请日：2014-03-11

    Applicant: KLA-TENCOR CORPORATION

    Inventor： SALEHPOUR, Ali ,  SINHA, Jaydeep K. ,  HALLER, Kurt ,  VUKKADALA, Pradeep ,  VAEZ-IRAVANI, Mehdi ,  KREN, George ,  ZHANG, Jiayao

    IPC: H01L21/66

    CPC classification number: G01B11/303 ,  G01B11/306 ,  G01B2210/56

    Abstract: A method of providing high accuracy inspection or metrology in a bright-field differential interference contrast (BF-DIC) system is described. This method can include creating first and second beams from a first light beam. The first and second beams have round cross-sections, and form first partially overlapping scanning spots radially displaced on a substrate. Third and fourth beams are created from the first light beam or a second light beam. The third beam and the fourth beam have elliptical cross-sections, and form second partially overlapping scanning spots tangentially displaced on the substrate. At least one portion of the substrate can be scanned using the first and second partially overlapping scanning spots as the substrate is rotated. Radial and tangential slopes can be determined using measurements obtained from the scanning using the first and second partially overlapping scanning spots. The radial and tangential slopes can be used to determine wafer shape or any localized topography feature.

    Abstract translation: 描述了在亮场差分干涉对比（BF-DIC）系统中提供高精度检测或计量的方法。 该方法可以包括从第一光束产生第一和第二光束。 第一和第二光束具有圆形横截面，并形成在衬底上径向位移的第一部分重叠的扫描点。 从第一光束或第二光束产生第三和第四光束。 第三光束和第四光束具有椭圆形截面，并形成在衬底上切向位移的第二部分重叠的扫描点。 当衬底旋转时，可以使用第一和第二部分重叠的扫描点来扫描衬底的至少一部分。 可以使用从使用第一和第二部分重叠的扫描点的扫描获得的测量来确定径向和切向斜率。 径向和切向斜率可用于确定晶片形状或任何局部地形特征。

    PREDICTIVE MODELING BASED FOCUS ERROR PREDICTION
    6.
    发明申请
    PREDICTIVE MODELING BASED FOCUS ERROR PREDICTION 审中-公开
    基于预测模型的焦点误差预测

    公开(公告)号：WO2016025037A1

    公开(公告)日：2016-02-18

    申请号：PCT/US2015/027254

    申请日：2015-04-23

    Applicant: KLA-TENCOR CORPORATION

    Inventor： VUKKADALA, Pradeep ,  SINHA, Jaydeep ,  CHANG, Wei ,  RAO, Krishna

    IPC: H01L21/66

    CPC classification number: B24B37/005 ,  B24B49/00 ,  G01B21/00 ,  G01B2210/48 ,  G03F7/705 ,  G03F9/7026 ,  G06N7/00 ,  G06N99/005

    Abstract: Predictive modeling based focus error prediction method and system are disclosed. The method includes obtaining wafer geometry measurements of a plurality of training wafers and grouping the plurality of training wafers to provide at least one training group based on relative homogeneity of wafer geometry measurements among the plurality of training wafers. For each particular training group of the at least one training group, a predictive model is develop utilizing non-linear predictive modeling. The predictive model establishes correlations between wafer geometry parameters and focus error measurements obtained for each wafer within that particular training group, and the predictive model can be utilized to provide focus error prediction for an incoming wafer belonging to that particular training group.

    Abstract translation: 公开了基于预测建模的聚焦误差预测方法和系统。 该方法包括获得多个训练晶片的晶片几何测量，并且基于多个训练晶片之间的晶片几何测量的相对均匀性，分组多个训练晶片以提供至少一个训练组。 对于至少一个训练组的每个特定训练组，利用非线性预测建模来开发预测模型。 该预测模型建立晶片几何参数和该特定训练组内的每个晶片获得的聚焦误差测量值之间的相关性，并且该预测模型可用于为属于该特定训练组的输入晶片提供聚焦误差预测。

    PATTERNED WAFER GEOMETRY MEASUREMENTS FOR SEMICONDUCTOR PROCESS CONTROLS
    7.
    发明申请
    PATTERNED WAFER GEOMETRY MEASUREMENTS FOR SEMICONDUCTOR PROCESS CONTROLS 审中-公开
    用于半导体工艺控制的图形波形几何测量

    公开(公告)号：WO2015199801A1

    公开(公告)日：2015-12-30

    申请号：PCT/US2015/027182

    申请日：2015-04-23

    Applicant: KLA-TENCOR CORPORATION

    Inventor： VUKKADALA, Pradeep ,  SINHA, Jaydeep

    IPC: H01L21/66

    CPC classification number: H01L22/12 ,  H01L22/20

    Abstract: Wafer geometry measurement tools and methods for providing improved wafer geometry measurements are disclosed. Wafer front side, backside and flatness measurements are taken into consideration for semiconductor process control. The measurement tools and methods in accordance with embodiments of the present disclosure are suitable for handling any types of wafers, including patterned wafers, without the shortcomings of conventional metrology systems.

    Abstract translation: 公开了用于提供改进的晶片几何测量的晶片几何测量工具和方法。 考虑半导体工艺控制时的晶片正面，背面和平坦度测量。 根据本公开的实施例的测量工具和方法适用于处理任何类型的晶片，包括图案化晶片，而没有传统测量系统的缺点。

    PROCESS-INDUCED DISTORTION PREDICTION AND FEEDFORWARD AND FEEDBACK CORRECTION OF OVERLAY ERRORS
    8.
    发明申请
    PROCESS-INDUCED DISTORTION PREDICTION AND FEEDFORWARD AND FEEDBACK CORRECTION OF OVERLAY ERRORS 审中-公开
    过程诱导失败预测和反馈纠正和反馈纠正重叠错误

    公开(公告)号：WO2015066232A1

    公开(公告)日：2015-05-07

    申请号：PCT/US2014/062992

    申请日：2014-10-29

    Applicant: KLA-TENCOR CORPORATION

    Inventor： VUKKADALA, Pradeep ,  CHEN, Haiguang ,  SINHA, Jaydeep ,  VEERARAGHAVAN, Sathish

    IPC: H01L21/66

    CPC classification number: G01N19/08 ,  C23C14/54 ,  G01L1/00 ,  G01L5/0047 ,  G03F7/705 ,  G03F7/70633 ,  G03F7/70783 ,  H01L22/12 ,  H01L22/20

    Abstract: Systems and methods for prediction and measurement of overlay errors are disclosed. Process-induced overlay errors may be predicted or measured utilizing film force based computational mechanics models. More specifically, information with respect to the distribution of film force is provided to a finite element (FE) model to provide more accurate point-by-point predictions in cases where complex stress patterns are present. Enhanced prediction and measurement of wafer geometry induced overlay errors are also disclosed.

    Abstract translation: 公开了用于预测和测量重叠误差的系统和方法。 可以使用基于薄膜力的计算力学模型来预测或测量过程引起的重叠误差。 更具体地，关于膜力的分布的信息被提供给有限元（FE）模型，以在存在复应力模式的情况下提供更准确的逐点预测。 还公开了晶片几何感应重叠误差的增强预测和测量。

    PATTERNED WAFER GEOMETRY MEASUREMENTS FOR SEMICONDUCTOR PROCESS CONTROLS
    10.
    发明公开
    PATTERNED WAFER GEOMETRY MEASUREMENTS FOR SEMICONDUCTOR PROCESS CONTROLS 审中-公开
    MESSUNGEN VON STRUKTURIERTER WAFERGEETTREFÜRHALBLEITERPROZESSSTEUERUNGEN

    公开(公告)号：EP3117454A1

    公开(公告)日：2017-01-18

    申请号：EP15811731.7

    申请日：2015-04-23

    Applicant: Kla-Tencor Corporation

    Inventor： VUKKADALA, Pradeep ,  SINHA, Jaydeep

    IPC: H01L21/66

    Abstract: Wafer geometry measurement tools and methods for providing improved wafer geometry measurements are disclosed. Wafer front side, backside and flatness measurements are taken into consideration for semiconductor process control. The measurement tools and methods in accordance with embodiments of the present disclosure are suitable for handling any types of wafers, including patterned wafers, without the shortcomings of conventional metrology systems.

    Abstract translation: 公开了用于提供改进的晶片几何测量的晶片几何测量工具和方法。 考虑半导体工艺控制的晶片前侧，背面和平坦度测量。 根据本公开的实施例的测量工具和方法适用于处理包括图案化晶片的任何类型的晶片，而不存在传统测量系统的缺点。

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