公开(公告)号：DE69916761T2

公开(公告)日：2004-09-23

申请号：DE69916761

申请日：1999-11-04

Applicant: KOREA ELECTRONICS TECHNOLOGY ,  PILKOR ELECTRONICS LTD

Inventor： KANG NAM KEE ,  PARK IN SHIG ,  LIM WOOK ,  YOO CHAN SEI ,  KIM JONG DAE ,  KO HYUN JONG ,  KIM SANG CHEOL

IPC: H01F17/00 ,  H01F27/34

Abstract: A multilayer type chip inductor includes a pair of outermost sheets each of which has a terminal pattern and a first via hole for an electrical connection with neighboring patterns and a plurality of intermediate sheets each of which has a conductor pattern, a second via hole for an electrical connection with neighboring patterns, and a first through hole for reducing a dielectric constant of the inductor. The intermediate sheets are stacked between the outermost sheets in such a way that the conductor patterns thereof are electrically connected with each other and simultaneously are electrically connected with the terminal patterns of the outermost sheets through the first and the second via holes.

公开(公告)号：DE69916761D1

公开(公告)日：2004-06-03

申请号：DE69916761

申请日：1999-11-04

Applicant: KOREA ELECTRONICS TECHNOLOGY ,  PILKOR ELECTRONICS LTD

Inventor： KANG NAM KEE ,  PARK IN SHIG ,  LIM WOOK ,  YOO CHAN SEI ,  KIM JONG DAE ,  KO HYUN JONG ,  KIM SANG CHEOL

IPC: H01F17/00 ,  H01F27/34

Abstract: A multilayer type chip inductor includes a pair of outermost sheets each of which has a terminal pattern and a first via hole for an electrical connection with neighboring patterns and a plurality of intermediate sheets each of which has a conductor pattern, a second via hole for an electrical connection with neighboring patterns, and a first through hole for reducing a dielectric constant of the inductor. The intermediate sheets are stacked between the outermost sheets in such a way that the conductor patterns thereof are electrically connected with each other and simultaneously are electrically connected with the terminal patterns of the outermost sheets through the first and the second via holes.