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公开(公告)号：DE69916761T2
公开(公告)日：2004-09-23
申请号：DE69916761
申请日：1999-11-04
Applicant: KOREA ELECTRONICS TECHNOLOGY , PILKOR ELECTRONICS LTD
Inventor： KANG NAM KEE , PARK IN SHIG , LIM WOOK , YOO CHAN SEI , KIM JONG DAE , KO HYUN JONG , KIM SANG CHEOL
Abstract: A multilayer type chip inductor includes a pair of outermost sheets each of which has a terminal pattern and a first via hole for an electrical connection with neighboring patterns and a plurality of intermediate sheets each of which has a conductor pattern, a second via hole for an electrical connection with neighboring patterns, and a first through hole for reducing a dielectric constant of the inductor. The intermediate sheets are stacked between the outermost sheets in such a way that the conductor patterns thereof are electrically connected with each other and simultaneously are electrically connected with the terminal patterns of the outermost sheets through the first and the second via holes.
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公开(公告)号：DE69916761D1
公开(公告)日：2004-06-03
申请号：DE69916761
申请日：1999-11-04
Applicant: KOREA ELECTRONICS TECHNOLOGY , PILKOR ELECTRONICS LTD
Inventor： KANG NAM KEE , PARK IN SHIG , LIM WOOK , YOO CHAN SEI , KIM JONG DAE , KO HYUN JONG , KIM SANG CHEOL
Abstract: A multilayer type chip inductor includes a pair of outermost sheets each of which has a terminal pattern and a first via hole for an electrical connection with neighboring patterns and a plurality of intermediate sheets each of which has a conductor pattern, a second via hole for an electrical connection with neighboring patterns, and a first through hole for reducing a dielectric constant of the inductor. The intermediate sheets are stacked between the outermost sheets in such a way that the conductor patterns thereof are electrically connected with each other and simultaneously are electrically connected with the terminal patterns of the outermost sheets through the first and the second via holes.
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公开(公告)号：KR20200139393A
公开(公告)日：2020-12-14
申请号：KR20190065859
申请日：2019-06-04
Applicant: KOREA ELECTRONICS TECHNOLOGY , LIM WOOK
Inventor： YOO CHAN SEI , LIM WOOK
Abstract: 자성체/유전체복합구조를적용한적층형칩 인덕터의구조및 이를구현하는기술이제공된다. 본발명의실시예에따른인덕터는자성체와유전체적층된복합구조체; 및복합구조체에적층된자성체와유전체를관통하는구조로형성된권선;을포함한다. 이에의해, 자성체와유전체를동시에적용한복합구조체를이용하여인덕터를구현함으로써, 기존자성체인덕터의품질계수를개선할수 있게된다.
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