公开(公告)号：KR20120060280A

公开(公告)日：2012-06-12

申请号：KR20100121449

申请日：2010-12-01

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： CHO YOUNG KYUN ,  JEON YOUNG DEUK ,  NAM JAE WON ,  KWON JONG KEE

IPC: H03M1/38

CPC classification number: H03M1/0621 ,  H03M1/38 ,  H03M2201/2233 ,  H03M2201/6107 ,  H03M2201/622

Abstract: PURPOSE: A SAR(Successive Approximation Register) ADC(Analog To Digital Converter) and an operation method thereof are provided to improve an operation speed of analog to digital conversion by optimizing latch movement. CONSTITUTION: An SAR(Successive Approximation Register) ADC(Analog To Digital Converter)(100) improves an operation speed in comparison with a general SAR ADC by using an asynchronous clock signal. The SAR ADC includes a digital conversion unit(110), an asynchronous clock generating circuit(120), and an SAR controller(130). The digital conversion unit changes an analog input voltage in response to a clock signal of the asynchronous clock generating circuit into digital signals. The asynchronous clock generating circuit generates the clock signal for controlling a sampling operation and a digital conversion operation in the digital conversion unit. The SAR controller controls the overall operation of the SAR ADC.

Abstract translation: 目的：提供SAR（逐次逼近寄存器）ADC（模数转换器）及其操作方法，通过优化锁存器移动来提高模数转换的操作速度。 构成：通过使用异步时钟信号，SAR（逐次逼近寄存器）ADC（模数转换器）（100）可以提高与通用SAR ADC相比的运行速度。 SAR ADC包括数字转换单元（110），异步时钟发生电路（120）和SAR控制器（130）。 数字转换单元响应于异步时钟产生电路的时钟信号将模拟输入电压改变成数字信号。 异步时钟产生电路产生用于控制数字转换单元中的采样操作和数字转换操作的时钟信号。 SAR控制器控制SAR ADC的整体运行。

公开(公告)号：KR20120064503A

公开(公告)日：2012-06-19

申请号：KR20100125773

申请日：2010-12-09

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： NAM JAE WON ,  JEON YOUNG DEUK ,  CHO YOUNG KYUN ,  KWON JONG KEE

IPC: H03M1/12

CPC classification number: H03M1/069 ,  H03M1/168 ,  H03M1/12 ,  H03M13/6502

Abstract: PURPOSE: A pipelined ADC(Analog To Digital Converter) is provided to minimize errors in a conversion stage by arranging a pipeline conversion stage error measurement and correction circuit. CONSTITUTION: A conversion stage circuit(1100) includes an upper conversion part(1100a) and a lower conversion part(1100b). A first digital correction circuit(1200) performs a logic correction motion by receiving digital codes outputted from the lower conversion part. The first digital correction circuit outputs M bits of corrected digital codes. A pipeline conversion stage error measurement and correction circuit(1300) corrects extracted errors by measuring conversion stage gains and offset errors in a first conversion stage. A second digital correction circuit(1400) finally outputs N bits of the digital codes by receiving the M bits of the digital codes. A clock signal generator(1500) generates clock signals necessary for digital conversion. A reference voltage buffer(1600) generates a reference voltage necessary for the digital conversion.

Abstract translation: 目的：提供流水线ADC（模数转换器），通过布置流水线转换级误差测量和校正电路来最大限度地减少转换阶段的误差。 构成：转换级电路（1100）包括上转换部（1100a）和下转换部（1100b）。 第一数字校正电路（1200）通过接收从下转换部分输出的数字代码来执行逻辑校正运动。 第一数字校正电路输出M位校正数字码。 流水线转换级误差测量和校正电路（1300）通过在第一转换级中测量转换级增益和偏移误差来校正提取的误差。 第二数字校正电路（1400）最后通过接收数字代码的M位来输出数字代码的N位。 时钟信号发生器（1500）产生数字转换所需的时钟信号。 参考电压缓冲器（1600）产生数字转换所需的参考电压。

公开(公告)号：KR20120065806A

公开(公告)日：2012-06-21

申请号：KR20100127115

申请日：2010-12-13

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： JEON YOUNG DEUK ,  CHO YOUNG KYUN ,  NAM JAE WON ,  KWON JONG KEE

IPC: H03M1/12 ,  H03M1/38

CPC classification number: H03M1/164 ,  H03M1/468 ,  H03M1/12 ,  H03M13/6502

Abstract: PURPOSE: An ADC(Analog To Digital Converter) is provided to shorten digital conversion time by performing an analog to digital conversion during a sampling period. CONSTITUTION: A first capacitor array(211) samples an analog input voltage. The first capacitor array includes a plurality of capacitors and a plurality of switches A first comparator(212) is connected to the analog input voltage through a sub ADC coupling circuit(215). The first comparator is connected to the first capacitor array through a main ADC coupling circuit(216). The first comparator transfers a comparison signal of a received signal to a first SAR logic circuit(213). The first SAR logic circuit determines a digital bit by one bit unit by receiving the comparison signal. The sub ADC coupling circuit and the main ADC coupling circuit are composed of a switch, respectively.

Abstract translation: 目的：提供一个ADC（模数转换器），通过在采样周期内执行模数转换来缩短数字转换时间。 构成：第一个电容阵列（211）对模拟输入电压进行采样。 第一电容器阵列包括多个电容器和多个开关。第一比较器（212）通过子ADC耦合电路（215）连接到模拟输入电压。 第一比较器通过主ADC耦合电路（216）连接到第一电容器阵列。 第一比较器将接收信号的比较信号传送到第一SAR逻辑电路（213）。 第一SAR逻辑电路通过接收比较信号来确定数字比特单位比特单位。 子ADC耦合电路和主ADC耦合电路分别由开关组成。