公开(公告)号：JPH09181275A

公开(公告)日：1997-07-11

申请号：JP21739496

申请日：1996-08-19

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： JIYONSUN RIYUU ,  UONGU KAN ,  KIYUUHON RII

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To integrate a transmission gate and a capacitor in a narrow DRAM cell area by a method wherein a capacitor electrode is positioned under the source of the transmission gate, a dielectric film is positioned under the capacitor electrode, and a plate electrode is positioned under the dielectric film. SOLUTION: A silicon on an insulator(SOT) transistor is used as a transmission gate, and a capacitor is provided with a capacitor electrode 82, a dielectric 89 and a plate electrode 88. The capacitor electrode 82 is arranged under the source 91 of the transmission gate, the dielectric 89 is arranged under the capacitor electrode 82, and the plate electrode 88 is arranged under the dielectric 89. By arranging the capacitor under the lower region of the transmission gate as above-mentioned, the transmission gate and the capacitor can be integrated in the narrow area of a dynamic random access memory(DRAM) cell.

公开(公告)号：JPH09181314A

公开(公告)日：1997-07-11

申请号：JP21554396

申请日：1996-08-15

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： JIYONHO RII ,  UONGU KAN ,  JIYONSUN RIYUU

IPC: H01L29/78 ,  H01L21/335 ,  H01L21/336

Abstract: PROBLEM TO BE SOLVED: To highly integrate a semiconductor device by a method wherein a gate electrode is made to self-align with a channel region, and at the same time the width of the gate electrode is minimized. SOLUTION: A second aperture 16 is formed in such a way that the upper part of a channel formation region is exposed, a polysilicon film 18 is deposited on the front surface of a nitride film 13, this polysilicon film 18 is pattered to make the polysilicon film 18 remain only in the interior of the aperture 16 and this remained polysilicon film 18 is formed on a gate electrode 21 so that the electrode 20 may be self-aligned with a channel region. This can realized that the width of a gate electrode 20 is minimized.

公开(公告)号：JPH09181083A

公开(公告)日：1997-07-11

申请号：JP21554296

申请日：1996-08-15

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIYUUHON RII ,  JINHIYOO RII ,  JIYONSUN RIYUU

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/70 ,  H01L29/732

Abstract: PROBLEM TO BE SOLVED: To eliminate a step of defining a base electrode from a structure of an existing pillar type bipolar transistor to minimize a parasitic capacitance of the base electrode. SOLUTION: First and second pillars 100A and 100B formed within first and second trenches 62A and 62B are used as active and collector regions respectively, the trenches 62A and 62B are formed at their bottoms with impurity layers 63 of a second conduction type having a high concentration as collector layers. In the first pillar, a base layer 66 and an emitter layer 72 are sequentially formed. Further formed within the first trench 62A is a base contact electrode 68 which is connected to the base layer 66. Impurities of the second conduction type are implanted to form a collector contact electrode 65.