公开(公告)号：JPH03228370A

公开(公告)日：1991-10-09

申请号：JP25402090

申请日：1990-09-21

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： RI KIKOU ,  KIN DAIYOU ,  RI CHINKOU ,  KIN SENSHIYU

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: PURPOSE: To improve capacitor area efficiency by making a transfer transistor first, forming bit lines, then forming an oxide film lattice with minimum line width between cells and forming single or double cup-shaped polysilicon storage electrode. CONSTITUTION: An activated region is defined, and a transistor is formed by LOCOS or SWAMI method on a silicon substrate 1. Next, a polycide layer 10 for bit line is formed, and a silicon nitride film 11 as an etch stop layer is formed. Moreover, etching is performed and a grid-shaped oxide film 16 is formed to a minimum line width, while defining a contact position 15 between the source portion of a transistor and a storage electrode. Next, a polysilicon electrode 17 is formed, a liquid photosensitive film 18 is coated, an upper end portion of the polysilicon electrode 17 is etched, and a cup-shaped storage electrode is formed. Next, the photosensitive film 18 is removed, and a dielectric film 19 for capacitor and a plate electrode 20 are formed for completion. As a result of this, the area can be increased, while the height of storage electrode can be made the largest, thereby increasing the area efficiency.