公开(公告)号：JPH05182959A

公开(公告)日：1993-07-23

申请号：JP33062091

申请日：1991-12-13

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： RI KIKOU ,  KIN DAIYOU ,  KIN OUSHIYU

IPC: H01L21/76 ,  H01L21/316

Abstract: PURPOSE: To provide an element isolating method with good electric characteristics even for the isolation of a 0.5 μm design role essential to the development of a highly integrated element of >=16 M bits as one of isolating methods utilizing a silicon substrate by making good use of polysilicon and eliminating a bird's beak generated by a LOCOS method. CONSTITUTION: This is a method which uses polysilicon as a material of silicon at the time of oxidation so as to form oxide for element separation; and an oxide film 12 is grown on the silicon substrate 11 and a nitride film 13 is formed to form a nitride film pattern as well as the LOCOS method. After oxide grown by etching and oxidizing a polysilicon film 15 is etched to above the nitride film by utilizing an etching baking process, the nitride film and oxide film are etched similarly to the advance in the LOCOS process to form the oxide for element separation.

公开(公告)号：JPH03180066A

公开(公告)日：1991-08-06

申请号：JP22953590

申请日：1990-08-29

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： RI KIKOU ,  KIN DAIYOU ,  RI CHINKOU ,  KIN SENJIYU

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: PURPOSE: To enlarge the area of a storage capacitor by depositing n polysilicon on a dielectric layer while coupling with an n diffused layer around a trench and on the bottom thereof thereby forming a plate. CONSTITUTION: After forming a primary dielectric layer 43a for capacitor in a trench, n doped polysilicon is deposited to form a secondary dielectric layer 43b. Subsequently, polysilicon is deposited thereon continuously to an n diffused layer around a trench and on the bottom thereof thus forming a plate 45. Since the capacitor between a polysilicon storage electrode 41 and the n diffusion plate 45, as well as the capacitor between the n polysilicon storage electrode 41 and the n diffused plate 45, can be utilized entirely as a storage capacitor, surface efficiency of the storage capacitor can be enhanced.

公开(公告)号：JPH05342871A

公开(公告)日：1993-12-24

申请号：JP34420092

申请日：1992-12-24

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： GO SHIYOUJIYUN ,  KEN SUIKI ,  SOU GENTETSU ,  KIN OUCHIYUU ,  KIN DAIYOU

IPC: G11C11/409 ,  G11C11/40

Abstract: PURPOSE: To reduce the delay time of a sensing operation by switch transistor for permitting assigning a load transistor pair of a sense amplifier group to each sense amplifier and providing a switch transistor which separates the output node of the amplifier and a main amplifier. CONSTITUTION: The output signal waveform of a column decoder 120 is delayed for a time required for permitting a signals of the output node pair 111 and 112 in a sense back-up circuit 100 to reach a prescribed reference level by a delay element 17 which is connected between an output node pairs 113 and 114 being different from plural sense amplifiers so as to be added to the gates of transistors Tr 15 and 16. Thus, Trs 15 and 16 are made to be in a conductive state, metallic line parasite capacitances 10 and 20 are connected to the nodes 111 and 112, the voltage of the node 111 is rapidly lowered and the voltage of the node 112 is lowered relatively gradually. Then, the main amplifier 30 is operated when control signals CNTL1 and CNTL2 are inputted and the voltages of the nodes 113 and 114 are instantaneously separated.

公开(公告)号：JPH03228370A

公开(公告)日：1991-10-09

申请号：JP25402090

申请日：1990-09-21

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： RI KIKOU ,  KIN DAIYOU ,  RI CHINKOU ,  KIN SENSHIYU

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: PURPOSE: To improve capacitor area efficiency by making a transfer transistor first, forming bit lines, then forming an oxide film lattice with minimum line width between cells and forming single or double cup-shaped polysilicon storage electrode. CONSTITUTION: An activated region is defined, and a transistor is formed by LOCOS or SWAMI method on a silicon substrate 1. Next, a polycide layer 10 for bit line is formed, and a silicon nitride film 11 as an etch stop layer is formed. Moreover, etching is performed and a grid-shaped oxide film 16 is formed to a minimum line width, while defining a contact position 15 between the source portion of a transistor and a storage electrode. Next, a polysilicon electrode 17 is formed, a liquid photosensitive film 18 is coated, an upper end portion of the polysilicon electrode 17 is etched, and a cup-shaped storage electrode is formed. Next, the photosensitive film 18 is removed, and a dielectric film 19 for capacitor and a plate electrode 20 are formed for completion. As a result of this, the area can be increased, while the height of storage electrode can be made the largest, thereby increasing the area efficiency.