公开(公告)号：FR2742614A1

公开(公告)日：1997-06-20

申请号：FR9614945

申请日：1996-12-05

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： JUNG HEE YOUNG ,  LEE BHUM CHEOL ,  PARK KWON CHUL

IPC: H04L7/00 ,  H04L7/02 ,  H04L7/033 ,  H04L7/04

Abstract: The apparatus a multiphase clock pulse generator (201) from which a pulse to synchronise incoming transmission signals is selected. Re-synchronisation is performed by a clock pulse selector (202). The selector finds clock pulses which are near to the edges of the transmission pulse sequences and a re-synchronisation synthesiser (203) synchronises the incoming transmissions using the selected pulses. The re-synchronised words are output by an output buffer.

公开(公告)号：GB2265284B

公开(公告)日：1995-11-01

申请号：GB9305529

申请日：1993-03-17

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： LEE BHUM CHEOL ,  PARK KWON CHUL ,  BAHK HANG GU

IPC: H03L7/089 ,  H03L7/093 ,  H03L7/107 ,  H03L7/14 ,  H04L7/00 ,  H04L7/033 ,  H03L7/087

Abstract: A bit synchronizer for NRZ data wherein a loop gain of a phase locked loop in the bit synchronizer is not varied sensitively to bit pattern and rate of the NRZ data and a voltage control led oscillator in the bit synchronizer oscillates synchronously with a multiple of a frequency of an external reference clock pulse even in the absence of NRZ data transitions or over a wide range of variation of a clock frequency of the voltage controlled oscillator, so that the NRZ data and clock can be recovered stably, According to the invention, the bit synchronizer comprises a phase comparator, a first gain controller, a frequency comparator, a second gain controller, a N-frequency divider, a low pass filter and a voltage controlled oscillator.

公开(公告)号：GB2265284A

公开(公告)日：1993-09-22

申请号：GB9305529

申请日：1993-03-17

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： LEE BHUM CHEOL ,  PARK KWON CHUL ,  BAHK HANG GU

IPC: H03L7/089 ,  H03L7/093 ,  H03L7/107 ,  H03L7/14 ,  H04L7/00 ,  H04L7/033

Abstract: A bit synchronizer for NRZ data wherein a loop gain of a phase locked loop in the bit synchronizer is not varied sensitively to bit pattern and rate of the NRZ data and a voltage controlled oscillator in the bit synchronizer oscillates synchronously with a multiple of a frequency of an external reference clock pulse oven in the absence of NRZ data transitions or over a wide range of variation of a clock frequency of the voltage controlled oscillator, so that the NRZ data and clock can be recovered stably. According to the invention, the bit synchronizer comprises a phase comparator (21), a first gain controller (22), a frequency comparator (23), a second gain controller (24), a N-frequency divider (25), a low pass filter (26) and a voltage controlled oscillator (27). The first and second gain controllers limit the gains of the place and frequency comparators, respectively, to predetermined values.

公开(公告)号：KR20120070905A

公开(公告)日：2012-07-02

申请号：KR20100132428

申请日：2010-12-22

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： BAEK DONG MYOUNG ,  CHOI KANG IL ,  LEE BHUM CHEOL ,  LEE JUNG HEE ,  OH SANG YOON ,  LEE SEUNG WOO ,  PARK YOUNG HO

IPC: H04L29/06

CPC classification number: H04L69/32

Abstract: PURPOSE: A distributed processing method and apparatus for multi-layer data using priority processing of layer 7 payload are provided to efficiently process a higher layer by properly distributing and arranging a higher layer throughput and a lower layer throughput. CONSTITUTION: A distributed processing apparatus(100) for multi-layer data integrally processes data having a multi-layer structure. The distributed processing apparatus prioritizes a higher layer prior to a lower layer in order to efficiently process data flow consisting of multi-layers. The distributed processing apparatus for multi-layer includes a higher layer processing unit(110) and a lower layer processing unit(120). The higher layer processing unit processes upper layer data flow generated by using higher layer information. The lower layer processing unit processes data flow received by using lower layer information into lower layer data flow.

Abstract translation: 目的：提供使用层7有效载荷的优先级处理的多层数据的分布式处理方法和装置，以通过适当地分配和布置更高层吞吐量和更低层吞吐量来有效地处理较高层。 构成：用于多层数据的分布式处理装置（100）整体处理具有多层结构的数据。 分布式处理装置在较低层之前对较高层进行优先级排序，以便有效地处理由多层组成的数据流。 用于多层的分布式处理装置包括较高层处理单元（110）和下层处理单元（120）。 较高层处理单元处理通过使用较高层信息生成的上层数据流。 下层处理单元通过使用较低层信息接收的数据流处理成较低层数据流。

公开(公告)号：KR20120060592A

公开(公告)日：2012-06-12

申请号：KR20100122179

申请日：2010-12-02

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： OH SANG YOON ,  BAEK DONG MYOUNG ,  LEE SEUNG WOO ,  CHOI KANG IL ,  LEE BHUM CHEOL ,  PARK YOUNG HO

IPC: H04L12/26 ,  G06F15/16

CPC classification number: H04L43/04 ,  G06F15/16

Abstract: PURPOSE: A packet inspection apparatus and method thereof are provided to effectively execute parallel processing by minimizing numbers of a bottleneck phenomenon in the communication of a pattern processor. CONSTITUTION: A pattern providing processor(110) manages plural patterns through connection lists including priority. The pattern providing processor provides plural patterns. Plural pattern inspection processors(120~140) inspects a correlation between inputted patterns and plural patterns. The pattern providing processor divides the patterns into a pattern groups. The pattern providing processor successively allocates the divided pattern group to the pattern providing processors according to the connection lists.

Abstract translation: 目的：提供一种分组检查装置及其方法，通过使图形处理器的通信中的瓶颈现象的数量最小化来有效地执行并行处理。 构成：图案提供处理器（110）通过包括优先级的连接列表管理多个模式。 图案提供处理器提供多种图案。 多种图案检查处理器（120〜140）检查输入图案与多种图案之间的相关性。 图案提供处理器将图案划分为图案组。 模式提供处理器根据连接列表将划分的模式组依次分配给模式提供处理器。

公开(公告)号：KR20120029680A

公开(公告)日：2012-03-27

申请号：KR20100091631

申请日：2010-09-17

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： OH SANG YOON ,  BAEK DONG MYOUNG ,  LEE JUNG HEE ,  LEE SEUNG WOO ,  LEE BHUM CHEOL ,  PARK YOUNG HO

IPC: H04L12/801 ,  H04L12/70 ,  H04L12/927

CPC classification number: H04L47/19 ,  H04L47/805 ,  H04L2012/5679

Abstract: PURPOSE: A packet scheduling device and a method thereof are provided to connect tuple state information with a processor identifier without a hash function, thereby increasing speed of scheduling packet data in a processor. CONSTITUTION: A processor allocating unit(210) allocates a packet to one of processors according to a comparison result of an information comparing unit. An information statistical unit(240) stores the number of packets which are processed per at least one processor. The information statistical unit selects one processor which minimally processes the packet. The information statistical unit provides a result to the processor allocating unit.

Abstract translation: 目的：提供一种分组调度设备及其方法，用于将元组状态信息与处理器标识符相连，而不需要散列函数，从而提高处理器中分组数据的调度速度。 构成：根据信息比较单元的比较结果，处理器分配单元（210）向一个处理器分配分组。 信息统计单元（240）存储根据至少一个处理器处理的分组数。 信息统计单元选择一种处理该数据包的处理器。 信息统计单元向处理器分配单元提供结果。