公开(公告)号：GB2265284B

公开(公告)日：1995-11-01

申请号：GB9305529

申请日：1993-03-17

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： LEE BHUM CHEOL ,  PARK KWON CHUL ,  BAHK HANG GU

IPC: H03L7/089 ,  H03L7/093 ,  H03L7/107 ,  H03L7/14 ,  H04L7/00 ,  H04L7/033 ,  H03L7/087

Abstract: A bit synchronizer for NRZ data wherein a loop gain of a phase locked loop in the bit synchronizer is not varied sensitively to bit pattern and rate of the NRZ data and a voltage control led oscillator in the bit synchronizer oscillates synchronously with a multiple of a frequency of an external reference clock pulse even in the absence of NRZ data transitions or over a wide range of variation of a clock frequency of the voltage controlled oscillator, so that the NRZ data and clock can be recovered stably, According to the invention, the bit synchronizer comprises a phase comparator, a first gain controller, a frequency comparator, a second gain controller, a N-frequency divider, a low pass filter and a voltage controlled oscillator.

公开(公告)号：GB2265284A

公开(公告)日：1993-09-22

申请号：GB9305529

申请日：1993-03-17

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： LEE BHUM CHEOL ,  PARK KWON CHUL ,  BAHK HANG GU

IPC: H03L7/089 ,  H03L7/093 ,  H03L7/107 ,  H03L7/14 ,  H04L7/00 ,  H04L7/033

Abstract: A bit synchronizer for NRZ data wherein a loop gain of a phase locked loop in the bit synchronizer is not varied sensitively to bit pattern and rate of the NRZ data and a voltage controlled oscillator in the bit synchronizer oscillates synchronously with a multiple of a frequency of an external reference clock pulse oven in the absence of NRZ data transitions or over a wide range of variation of a clock frequency of the voltage controlled oscillator, so that the NRZ data and clock can be recovered stably. According to the invention, the bit synchronizer comprises a phase comparator (21), a first gain controller (22), a frequency comparator (23), a second gain controller (24), a N-frequency divider (25), a low pass filter (26) and a voltage controlled oscillator (27). The first and second gain controllers limit the gains of the place and frequency comparators, respectively, to predetermined values.

公开(公告)号：FR2742614A1

公开(公告)日：1997-06-20

申请号：FR9614945

申请日：1996-12-05

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： JUNG HEE YOUNG ,  LEE BHUM CHEOL ,  PARK KWON CHUL

IPC: H04L7/00 ,  H04L7/02 ,  H04L7/033 ,  H04L7/04

Abstract: The apparatus a multiphase clock pulse generator (201) from which a pulse to synchronise incoming transmission signals is selected. Re-synchronisation is performed by a clock pulse selector (202). The selector finds clock pulses which are near to the edges of the transmission pulse sequences and a re-synchronisation synthesiser (203) synchronises the incoming transmissions using the selected pulses. The re-synchronised words are output by an output buffer.

公开(公告)号：DE3941252A1

公开(公告)日：1990-06-21

申请号：DE3941252

申请日：1989-12-14

Applicant: ELECTRONIC & TELECOMM RES INST ,  KOREA TELECOMMUNICATION

Inventor： LEE BHUM CHEOL ,  PARK KWON CHUL ,  KIM BONG TAE

IPC: H04L7/00 ,  H04J3/06 ,  H04L7/08

Abstract: A reframe circuit in a synchronous multiplexing device comprising a frame synchronizing pattern detection circuit, a frame pattern bit error detection circuit responsive to a serial data stream from the frame synchronizing pattern detection circuit, an in-frame/out-of-frame state discrimination circuit responsive to the output signal from the frame pattern bit error detection circuit and the output signal from the synchronizing pattern detection circuit, a counter phase synchronizing circuit responsive to the output signal from the in-frame/out-of-frame state discrimination circuit, the output signal from the frame synchronization pattern detection circuit and a reference phase signal, and a counter and timing generation circuit responsive to the operating mode control signal from the counter phase synchronizing circuit.

公开(公告)号：KR100786387B1

公开(公告)日：2007-12-17

申请号：KR20060071513

申请日：2006-07-28

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIM BYOUNG WHI ,  KANG BYUNG YONG ,  PARK KWON CHUL ,  WON JEONG WOOK

IPC: H04B7/26 ,  G01S5/02 ,  G01S5/10

CPC classification number: G01S5/0294 ,  G01S19/24 ,  H04W4/02

Abstract: A real-time location tracking method is provided to enable a user to demand location tracking to a tracked terminal through a tracking terminal, so that the tracked terminal can offer location information in real time according to the demand. A tracked terminal(120) combined with a mobile communication function and a GPS(Global Positioning System) function in integrated type receives a GPS signal to calculate location information in real time. A transmission request for the location information on the tracked terminal(120) from a tracking terminal(140) is decided on. If the request exists, the location information and an intrinsic ID are transmitted to the tracking terminal(140). It is decided whether a transmission mode for transmitting the location information and the ID is an automatic mode or a manual mode. In case of the automatic mode, it is decided whether the transmission mode is a transmission period mode. If so, and if a preset transmission period elapses, the location information and the ID are transmitted to the tracking terminal(140).

Abstract translation: 提供了一种实时位置跟踪方法，使得用户能够通过跟踪终端向跟踪终端请求定位跟踪，使得跟踪的终端可以根据需要实时提供位置信息。 结合移动通信功能的跟踪终端（120）和集成型的GPS（全球定位系统）功能接收GPS信号以实时计算位置信息。 确定来自跟踪终端（140）的跟踪终端（120）上的位置信息的发送请求。 如果存在请求，则将位置信息和固有ID发送到跟踪终端（140）。 确定用于发送位置信息和ID的传输模式是自动模式还是手动模式。 在自动模式的情况下，确定传输模式是传输周期模式。 如果是，则如果经过了预设的传输周期，则将位置信息和ID发送到跟踪终端（140）。

公开(公告)号：DE3942431A1

公开(公告)日：1990-06-28

申请号：DE3942431

申请日：1989-12-21

Applicant: ELECTRONIC & TELECOMM RES INST ,  KOREA TELECOMMUNICATION

Inventor： LEE BHUM CHEOL ,  PARK KWON CHUL

IPC: H03L7/00 ,  H04L7/00 ,  H04L7/027 ,  H04L7/033 ,  H04L25/40

Abstract: From the clock signal of a voltage controlled oscillator there is derived a true and a phase-inverted clock. A synchroniser device synchronises NRZ data received at the input, with the true and inverse clock. A first circuit forms the phase difference between the NRZ data received at the input, and that synchronised with the true clock. A second circuit forms the phase difference between the NRZ data synchronised with the phase inverted clock and that synchronised with the phase-true clock. The outputs of the two circuits are compared together to form a phase difference, and this is used to determine the phase and frequency. Logic circuitry is described, using D flip-flop and exclusive OR gates. ADVANTAGE - Reduced jitter, in circuit using standard elements.