公开(公告)号：JPH05347317A

公开(公告)日：1993-12-27

申请号：JP34485591

申请日：1991-12-26

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： BOKU TETSUJIYUN ,  CHIN KIKAN ,  MOU SEIZAI ,  YOU TENKIYOKU ,  SAI EIKEI ,  KIYOU CHINEI ,  RI KEIKOU ,  RI SHINHI ,  KIN DOUCHIN

IPC: H01L29/812 ,  H01L21/285 ,  H01L21/338

Abstract: PURPOSE: To improve a resistance characteristic by using a double-layered heat-resistant gate obtained by forming a heat-resistant junction material on the surface of a GaAs substrate and forming a metal having a low resistance on the junction material. CONSTITUTION: N-type impurities 121a are ion-implanted into an active-layer region of a GaAs substrate 121 with the pattern of a photosensitive film 124 as a mask. Next, the photosensitive film 124 is removed, and a silicon layer 122 and a metallic layer 123 are sequentially deposited. Then, a double layer comprising a metal layer 123a and a silicon layer 122a is formed by an etching process. Then, highly concentrated n-type impurities 121b are ion-implanted into a source/drain region, within the active region of the double layer. After the implantation, heat treatment is performed to cause a chemical reaction. By this treatment, a part of the metallic layer 123 in contact with the silicon layer 122 changes into a metallic silicide layer 125. Then, an ohmic electrode 126 is formed, and the device is completed. Thus, the gate has a low resistance.

公开(公告)号：JPH0645361A

公开(公告)日：1994-02-18

申请号：JP34486191

申请日：1991-12-26

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： BOKU TETSUJIYUN ,  CHIN KIKAN ,  MOU SEIZAI ,  YOU TENKIYOKU ,  SAI EIKEI ,  KIYOU CHINEI ,  RI KEIKOU ,  RI SHINHI ,  KIN DOUCHIN

IPC: H01L21/22 ,  H01L21/225 ,  H01L21/265 ,  H01L21/285 ,  H01L21/338 ,  H01L29/812

Abstract: PURPOSE: To allow silicon ions within an evaporated silicon thin film to the diffused into a substrate, even by implanting small amounts of low-energy ions and by heat treatment. CONSTITUTION: A method of manufacturing a GaAs metal-semiconductor field effect transistor involves the steps of: forming a silicon layer 2 on a GaAs substrate 1, forming a first photoresist pattern 3 on the silicon layer 2 using a known image inversion method to define an ohmic contact for source/drain electrodes and etching a silicon layer portion excluding the ohmic contact using photolithography, defining a channel region by forming a second photoresist pattern 4 on the substrate 1 after the first photoresist pattern 3 has been removed, and forming a channel region 5 by implanting a prescribed amount of silicon ions Si into the substrate 1, using the second photoresist pattern 4 as a mask.