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公开(公告)号:JPH07202873A
公开(公告)日:1995-08-04
申请号:JP29122694
申请日:1994-11-25
Applicant: KOREA ELECTRONICS TELECOMM
Inventor: SAI SOUKUN , BOKU FUMIHARU , KAKU MEISHIN , SAI KAIKIYOKU
Abstract: PURPOSE: To supply a stabilized cock even when the input of a data signal or power supply is not normal. CONSTITUTION: When power is normally supplied and data signal is normally inputted, a loop selection switch 30 outputs a state '1' and a 1st loop circuit is selected. At this time, the phase of the data signal is compared with a clock outputted from a voltage controlled oscillator(VCO) 4 and a synchronizing clock is generated. In the case of restoring the system after a short-circuiting of a transmission line, the transmission interruption of a data signal or the interruption of power supply, a data signal monitoring part 40 or a power supply monitoring part 50 outputs a state '1', so that the switch 30 selects a 2nd loop. Then the phase of a reference clock built in the system itself is compared with that of a clock outputted from a VCO 28 to generate a synchronizing clock.
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公开(公告)号:JPH07202705A
公开(公告)日:1995-08-04
申请号:JP29988094
申请日:1994-12-02
Applicant: KOREA ELECTRONICS TELECOMM
Inventor: SOU GENTETSU , GO SHIYOUJIYUN , RI SHIYOURETSU , SAI KAIKIYOKU , BAN SUTSUPU SON
Abstract: PURPOSE: To provide an accurate capacitor type voltage divider circuit having reduced power consumption by utilizing capacitor system instead of an existing resistor system. CONSTITUTION: Plural switching sections 311 to 313 are driver in accordance with predetermined 1st and 2nd clock signals 301, 305 and provide three reference voltage levels VR, VM, VSS to respective voltage divider capacitors 323, 324. A voltage divider section divides the reference voltage levels VR, VM, VSS to required values. In this case, output voltage (Vri) is expressed by Vri=(VR×Ci2+VSS×Ci1)/(Ci1+Ci2), where Ci1, Ci2 are voltage dividing capacitance values.
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公开(公告)号:JPH07202651A
公开(公告)日:1995-08-04
申请号:JP29977094
申请日:1994-12-02
Applicant: KOREA ELECTRONICS TELECOMM
Inventor: SOU GENTETSU , GO SHIYOUJIYUN , RI SHIYOURETSU , SAI KAIKIYOKU , BAN SUTSUPU SON
Abstract: PURPOSE: To suppress the consumption of currents by instantaneously changing the signal levels of two output terminals for outputting current signals when the logical level of a latch signal is changed, and in steady operation, outputting no current signal. CONSTITUTION: At the time of latch operation holding a latch signal LB at a high logical level, current signals I51, I52 converted by a signal conversion part 50 are supplied to transistors(TRs) Q81, Q82 in an amplification/ determination part 80 through TRs Q64, Q62 in a switching part 60. When the signal LB is at a low logical level and there is no latch operation, the voltage levels of output terminals OUT1, OUT2 are held at a high logical level by a high level holding part 70 to set up an output holding state. Only during a steady operation, a circuit current is turned to '0' by the output signal feedback of an output feedback part 90. Consequently only when the logical level of the signal LB is changed, the signal levels of the terminals OUT1, OUT2, are instantaneously changed and allowed to flow out from the comparator. Since there is no current outflow during stready operation, current consumption can be suppressed.
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