公开(公告)号：JPH02202734A

公开(公告)日：1990-08-10

申请号：JP32277389

申请日：1989-12-14

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： BOMU CHIYORU RII ,  KUUON CHIYORU PAKU ,  BON TE KIMU

IPC: H04L7/00 ,  H04J3/06 ,  H04L7/08

Abstract: PURPOSE: To attain extensive use with excellent synchronizing performance even for a non-standardized tramsmitting speed, and to improve data transmitting quality by providing a frame synchronizing pattern detecting means and a counter phase synchronizing means or the like. CONSTITUTION: A frame synchroniying pattern detecting circuit 1 outputs an output signal X to a counter phase synchronizing circuit 4 at the time of detecting the coincidence of a synchronizing pattern in a received data stream with a normalized synchronizing pattern. Also, a synchronizing/synchronization losing state deciding circuit 3 inputs an output signal FER indicating the detection in a synchronization losing state of the circuit 1, and an output signal BER of a frame pattern bit error detecting circuit 2, and outputs an output signal W to the circuit 4. The circuit 4 inputs the signal X, the signal W, and reference phase information Y of a counter and timing generating circuit 5, and outputs a control signal Z for operating the circuit 5 in a parallel load mode or count-up mode. Thus, extensive use can be attained with excellent synchronizing performance even for a non-standardized transmitting speed, and to improve transmitting quality.

公开(公告)号：JPH02202733A

公开(公告)日：1990-08-10

申请号：JP32277289

申请日：1989-12-14

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： BON TE KIMU

IPC: H04J3/06 ,  H04L7/00 ,  H04L7/04 ,  H04L7/08 ,  H04Q11/04

Abstract: PURPOSE: To widely use this circuit at a non-standardized transmitting speed and configuration, and to minimize transmission loss by quickly and effectively synchronizing the phase of a counter with the phase of a synchronihng pattern in a received serial bit stream. CONSTITUTION: A frame synchronizing pattern detecting part 1 transmits an output signal the inversion of X to a phase synchronizing circuit 2 at the time of detecting a preliminarily decided synchronizing pattern in a received serial bit stream. The circuit 2 inputs a signal from the detecting part 1 and a feedback signal the inversion of Y (existing phase information) from a counter 3, and turns an output signal Z into 0, and controls the counter 3 in a serial mode when a synchronizing pattern normalized in the prescribed period of the counter 3 is detected. That is, the phase of the counter 3 is quickly and efficiently synchronized with the phase of the synchronizing pattern included in the received serial bit stream through NOR gates 4 and 6, DFF 5, invertor T, and OR gate 8 in the circuit 2. Thus, this circuit can be widely used in a non-standardized transmitting speed and configuration, and transmission loss can be minimized.