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公开(公告)号：JPH02202734A
公开(公告)日：1990-08-10
申请号：JP32277389
申请日：1989-12-14
Applicant: KOREA ELECTRONICS TELECOMM , KOREA TELECOMMUNICATION
Inventor： BOMU CHIYORU RII , KUUON CHIYORU PAKU , BON TE KIMU
Abstract: PURPOSE: To attain extensive use with excellent synchronizing performance even for a non-standardized tramsmitting speed, and to improve data transmitting quality by providing a frame synchronizing pattern detecting means and a counter phase synchronizing means or the like. CONSTITUTION: A frame synchroniying pattern detecting circuit 1 outputs an output signal X to a counter phase synchronizing circuit 4 at the time of detecting the coincidence of a synchronizing pattern in a received data stream with a normalized synchronizing pattern. Also, a synchronizing/synchronization losing state deciding circuit 3 inputs an output signal FER indicating the detection in a synchronization losing state of the circuit 1, and an output signal BER of a frame pattern bit error detecting circuit 2, and outputs an output signal W to the circuit 4. The circuit 4 inputs the signal X, the signal W, and reference phase information Y of a counter and timing generating circuit 5, and outputs a control signal Z for operating the circuit 5 in a parallel load mode or count-up mode. Thus, extensive use can be attained with excellent synchronizing performance even for a non-standardized transmitting speed, and to improve transmitting quality.
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公开(公告)号：JPH0575589A
公开(公告)日：1993-03-26
申请号：JP10590791
申请日：1991-05-10
Applicant: KOREA ELECTRONICS TELECOMM , KOREA TELECOMMUNICATION
Inventor： BOMU CHIYORU RII , KUUON CHIYORU PAKU
Abstract: PURPOSE: To enable use for high-speed and low-speed electronic data transmission by comparing the outputs of a phase shift extracting means and a reference phase extracting means with each other and detecting a phase by a leading phase pulse generating means and a lagging phase pulse generating means. CONSTITUTION: The output of the phase shift extracting means U4 which is different in output pulse width according to the phase difference between the transition position of a retiming clock pulse and the bit interval center position of input NRZ data is compared with the output of the reference phase extracting means U5 to detect a phase on an analog basis. Further, the phase is detected on a digital basis by the leading phase pulse generating means U6 and lagging phase pulse generating means U7 which generate pulses when the transition of the retiming clock pulse is caused behind and before the bit interval center of the input NRZ data. With this constitution, the phase detector can be obtained which is usable for high-speed and low-speed electric data transmission and applicable to an analog PLL circuit and a digital PLL circuit.
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公开(公告)号：JPH0362645A
公开(公告)日：1991-03-18
申请号：JP32619589
申请日：1989-12-18
Applicant: KOREA ELECTRONICS TELECOMM , KOREA TELECOMMUNICATION
Inventor： BOMU CHIYORU RII , KUUON CHIYORU PAKU
Abstract: PURPOSE: To reduce jitter components by extracting phase difference between retimed NRZ data and inputted NRZ and extracting phase difference between the data retimed by the same phase and the opposite phase clocks. CONSTITUTION: A VCO clock is separated into the same and opposite clocks by the same phase and the opposite phase generating circuit U1. As the same phase clock is inputted to the clock terminal Cp of DFFU 2 and the opposite phase clock is inputted to the clock terminal P of DFFU 3, NZR data outputted from U2 and U3 is alternately retimed each time of the transition of the VCO clock. Consequently, concerning retimed NGR data outputted from the outputs Q of U2 and U3, the phase is advanced or delayed by 1/2 period of a VCO clock. Then, when the exclusive OR of the outputs Q of U2 and U3 are taken, a time interval pulse with the time interval of 1/2 period of VCO clock is generated form the output terminal of an exclusive OR gate U4b each time of the transition of NZR data.
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