公开(公告)号：GB2306716A

公开(公告)日：1997-05-07

申请号：GB9622841

申请日：1996-11-01

Applicant: KOREA TELECOMMUNICATION

Inventor： KIM KYEOUN SOO ,  JANG SOON HWA ,  KWON SOON HONG

IPC: G11C7/00 ,  G06F7/78 ,  G06F17/16 ,  G11C8/00 ,  G06F7/00

Abstract: A circuit for performing a bit-serial matrix transposition operation comprises an input shift register module 11 for inputting matrix elements of length k bits. The input shift register module 11 outputs the data in units of k/N bits and applies the units to a bit-serial transposition module 12. An output multiplexer module 13 selects k/N-bit data units from the bit-serial transposition module 12 in response to a switching control signal. An output register module 14 receives the data output from the output multiplexer module 13 in the k/N bit units and outputs N data in units of k bits which make up the transposed matrix.

公开(公告)号：GB2306716B

公开(公告)日：2000-02-16

申请号：GB9622841

申请日：1996-11-01

Applicant: KOREA TELECOMMUNICATION

Inventor： KIM KYEOUN SOO ,  JANG SOON HWA ,  KWON SOON HONG

IPC: G11C7/00 ,  G06F7/78 ,  G06F17/16 ,  G11C8/00 ,  G06F7/00

Abstract: A very large scale integrated circuit for performing a bit-serial matrix transposition operation, comprising an input shift register module for inputting N multiplied results of two NxN matrixes in the unit of k bits and outputting them in the unit of k/N bits in response to a load signal, a bit-serial transposition module for selecting k/N-bit data from the input shift register module in response to a switching control signal, an output multiplexer module for selecting k/N-bit data from the bit-serial transposition module in response to the switching control signal, and an output register module for inputting output data from the output multiplexer module in the unit of k/N bits and outputting N data in the unit of k bits. According to the present invention, when an NxN matrix transposition operation is performed, the operation occupancy of transposition cells becomes 100% after an N-input delay occurs. Also, the processing unit of data becomes smaller by using a bit-serial processing algorithm. Therefore, the high-speed operation can be performed. Further, the number of gates can be reduced in the integrated circuit. Moreover, because the integrated circuit has a pipelined structure, it is applicable to a multi-dimensional signal processing system requiring a high-speed processing operation.