SELECTIVE ETCH OF FILMS WITH HIGH DIELECTRIC CONSTANT
    1.
    发明申请
    SELECTIVE ETCH OF FILMS WITH HIGH DIELECTRIC CONSTANT 审中-公开
    具有高介电常数的薄膜的选择性蚀刻

    公开(公告)号:WO2005071722B1

    公开(公告)日:2005-11-17

    申请号:PCT/US2005001073

    申请日:2005-01-12

    CPC classification number: H01L29/517 H01L21/28194 H01L21/31116 H01L21/31122

    Abstract: A method for selectively etching a high dielectric constant layer over a silicon substrate is provided. The silicon substrate is placed into an etch chamber. An etchant gas is provided into the etch chamber, where the etchant gas comprises BCl3, an inert diluent, and Cl2, where the flow ratio of the inert diluent to BCl3 is between 2:1 and 1:2, and where the flow ratio of BCl3 to Cl2 is between 2:1 and 20:1. A plasma is generated from the etchant gas to selectively etch the high dielectric constant layer.

    Abstract translation: 提供了一种用于在硅衬底上选择性蚀刻高介电常数层的方法。 将硅衬底放置在蚀刻室中。 蚀刻气体被提供到蚀刻室中,其中蚀刻剂气体包括BCl 3,惰性稀释剂和Cl2,其中惰性稀释剂与BCl 3的流动比在2:1和1:2之间,其中流动比 BCl3至Cl2的含量为2:1至20:1。 从蚀刻剂气体产生等离子体以选择性地蚀刻高介电常数层。

    PROCESS CONTROLS FOR IMPROVED WAFER UNIFORMITY USING INTEGRATED OR STANDALONE METROLOGY

    公开(公告)号:MY131237A

    公开(公告)日:2007-07-31

    申请号:MYPI20045152

    申请日:2004-12-15

    Applicant: LAM RES CORP

    Abstract: A METHOD AND APPARATUS IS PROVIDED FOR MEASURING MULTIPLE LOCATIONS ON A WAFER (306) FOR CONTROLLING A SUBSEQUENT SEMICONDUCTOR-PROCESSING STEP TO ACHIEVE GREATER DIMENSIONAL UNIFORMITY ACROSS THAT WAFER. THE METHOD AND APPARATUS MAPS A DIMENSION OF A FEATURE AT MULTIPLE LOCATIONS TO CREATE A DIMENSION MAP (200), TRANSFORMS THE DIMENSION MAP INTO A PROCESSING PARAMETER MAP (502,504), AND USES THE PROCESSING PARAMETER MAP TO TAILOR THE SUBSEQUENT PROCESSING STEP TO THAT SPECIFIC WAFER. THE WAFER CAN ALSO BE MEASURED AFTER THE PROCESSING TO COMPARE AN ACTUAL OUTCOME WITH THE TARGETED OUTCOME, AND THE DIFFERENCE CAN BE USED TO REFINE THE TRANSFORMATION FROM A DIMENSION MAP TO A PROCESSING PARAMETER MAP FOR A SUBSEQUENT WAFER.(FIG 6)

Patent Agency Ranking