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    PROCESS CONTROLS FOR IMPROVED WAFER UNIFORMITY USING INTEGRATED OR STANDALONE METROLOGY
    1.
    发明申请
    PROCESS CONTROLS FOR IMPROVED WAFER UNIFORMITY USING INTEGRATED OR STANDALONE METROLOGY 审中-公开
    使用综合或STANDALONE METROLOGY改进WAFER均匀性的过程控制

    公开(公告)号：WO2005067009A3

    公开(公告)日：2005-08-18

    申请号：PCT/US2004042825

    申请日：2004-12-17

    Applicant: LAM RES CORP ,  KOTA GOWRI P ,  LUQUE JORGE

    Inventor： KOTA GOWRI P ,  LUQUE JORGE

    IPC: H01L21/00 ,  H01L21/66

    CPC classification number: H01L21/67253 ,  H01L22/20 ,  H01L2924/0002 ,  Y10S438/907 ,  H01L2924/00

    Abstract: A method and apparatus is provided for measuring multiple locations on a wafer for controlling a subsequent semiconductor processing step to achieve greater dimensional uniformity across that wafer. The method and apparatus maps a dimension of a feature at multiple locations to create a dimension map, transforms the dimension map into a processing parameter map, and uses the processing parameter map to tailor the subsequent processing step to that specific wafer. The wafer can also be measured after the processing to compare an actual outcome with the targeted outcome, and the difference can be used to refine the transformation from a dimension map to a processing parameter map for a subsequent wafer.

    Abstract translation: 提供了一种用于测量晶片上的多个位置的方法和装置，用于控制随后的半导体处理步骤以在该晶片上实现更大的尺寸均匀性。 该方法和装置将特征的维度映射到多个位置以创建维度图，将维度图变换为处理参数图，并使用处理参数图来定制到该特定晶片的后续处理步骤。 也可以在处理之后测量晶片以将实际结果与目标结果进行比较，并且该差异可用于细化从尺寸图到后续晶片的处理参数图的变换。

    METHOD AND SYSTEM FOR CENTERING WAFER ON CHUCK
    2.
    发明申请
    METHOD AND SYSTEM FOR CENTERING WAFER ON CHUCK 审中-公开
    用于在卡盘上定中晶片的方法和系统

    公开(公告)号：WO2010067284A2

    公开(公告)日：2010-06-17

    申请号：PCT/IB2009055503

    申请日：2009-12-04

    Applicant: LAM RES CORP ,  O'NEILL ROBERT GRIFFITH ,  LUQUE JORGE ,  CHOU SHANG-I ,  SINGH HARMEET

    Inventor： O'NEILL ROBERT GRIFFITH ,  LUQUE JORGE ,  CHOU SHANG-I ,  SINGH HARMEET

    IPC: H01L21/68 ,  H01L21/687

    CPC classification number: H01L21/67748 ,  G01N21/9501 ,  G01N2021/8864 ,  H01L21/67259 ,  H01L21/68

    Abstract: A wafer handling mechanism is operated to place a wafer on a chuck. A chucking force is then applied to the wafer, whereby wafer support features of the chuck transfer a defect pattern onto a surface of the wafer. The surface of the wafer is analyzed by a defect metrology tool to obtain a mapping of the defect pattern transferred onto the surface of the wafer. A center coordinate of the chuck within a coordinate system of the wafer is determined by analyzing the defect pattern as transferred to the surface of the wafer. A spatial offset between the center coordinate of the chuck and the center of the wafer is determined. The spatial offset is used to adjust the wafer handling mechanism so as to enable alignment of the center of the wafer to the center coordinate of the chuck.

    Abstract translation: 操作晶片处理机构以将晶片放置在卡盘上。 然后将夹紧力施加到晶片，由此夹盘的晶片支撑特征将缺陷图案转移到晶片的表面上。 通过缺陷度量工具分析晶片的表面，以获得转移到晶片表面上的缺陷图案的映射。 通过分析传送到晶片表面的缺陷图案来确定晶片的坐标系内的卡盘的中心坐标。 确定卡盘的中心坐标和晶片的中心之间的空间偏移。 空间偏移用于调整晶片处理机构，以使晶片的中心能够对准卡盘的中心坐标。

    USER INTERFACE FOR QUANTIFYING WAFER NON-UNIFORMITIES AND GRAPHICALLY EXPLORE SIGNIFICANCE
    3.
    发明申请
    USER INTERFACE FOR QUANTIFYING WAFER NON-UNIFORMITIES AND GRAPHICALLY EXPLORE SIGNIFICANCE 审中-公开
    用户界面用于量化晶圆非均匀性并以图形方式探索意义

    公开(公告)号：WO2004030083A3

    公开(公告)日：2004-07-15

    申请号：PCT/US0330456

    申请日：2003-09-24

    Applicant: LAM RES CORP

    Inventor： LUQUE JORGE ,  BAILEY III ANDREW D ,  WILCOXSON MARK

    IPC: H01L21/66

    CPC classification number: H01L22/20

    Abstract: A wafer viewer system is provided for graphical presentation and analysis of a wafer and a wafer series. More specifically, the wafer viewer system includes a graphical user interface for displaying a wafer, graphically selecting regions of the wafer for analysis, performing analysis on the selected regions of the wafer, and displaying results of the analysis.

    Abstract translation: 提供晶片查看器系统用于晶片和晶片系列的图形显示和分析。 更具体地，晶片观察器系统包括用于显示晶片的图形用户界面，以图形方式选择用于分析的晶片的区域，对晶片的选定区域执行分析，并且显示分析结果。

    PROCESS CONTROLS FOR IMPROVED WAFER UNIFORMITY USING INTEGRATED OR STANDALONE METROLOGY
    7.
    发明专利
    PROCESS CONTROLS FOR IMPROVED WAFER UNIFORMITY USING INTEGRATED OR STANDALONE METROLOGY 未知

    公开(公告)号：MY131237A

    公开(公告)日：2007-07-31

    申请号：MYPI20045152

    申请日：2004-12-15

    Applicant: LAM RES CORP

    Inventor： KOTA GOWRI ,  LUQUE JORGE

    IPC: H01L21/66 ,  H01L21/00

    Abstract: A METHOD AND APPARATUS IS PROVIDED FOR MEASURING MULTIPLE LOCATIONS ON A WAFER (306) FOR CONTROLLING A SUBSEQUENT SEMICONDUCTOR-PROCESSING STEP TO ACHIEVE GREATER DIMENSIONAL UNIFORMITY ACROSS THAT WAFER. THE METHOD AND APPARATUS MAPS A DIMENSION OF A FEATURE AT MULTIPLE LOCATIONS TO CREATE A DIMENSION MAP (200), TRANSFORMS THE DIMENSION MAP INTO A PROCESSING PARAMETER MAP (502,504), AND USES THE PROCESSING PARAMETER MAP TO TAILOR THE SUBSEQUENT PROCESSING STEP TO THAT SPECIFIC WAFER. THE WAFER CAN ALSO BE MEASURED AFTER THE PROCESSING TO COMPARE AN ACTUAL OUTCOME WITH THE TARGETED OUTCOME, AND THE DIFFERENCE CAN BE USED TO REFINE THE TRANSFORMATION FROM A DIMENSION MAP TO A PROCESSING PARAMETER MAP FOR A SUBSEQUENT WAFER.(FIG 6)

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