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    METHOD FOR FORMING GRADED OXIDE LAYER ON SILICON SUBSTRATE
    1.
    发明专利
    METHOD FOR FORMING GRADED OXIDE LAYER ON SILICON SUBSTRATE 失效

    公开(公告)号：JP2000323473A

    公开(公告)日：2000-11-24

    申请号：JP2000004078

    申请日：2000-01-12

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： CHEN YUANNING ,  MERCHANT SAILESH M ,  ROY PRADIP K

    IPC: H01L21/283 ,  C30B33/00 ,  H01L21/28 ,  H01L21/316 ,  H01L21/318 ,  H01L29/51 ,  H01L29/78

    Abstract: PROBLEM TO BE SOLVED: To form an oxide layer which includes graded portions with greatly reduced stress on a silicon substrate. SOLUTION: This method comprises a first step where a first oxide portion 31 is grown by upwardly ramping a silicon substrate 22 to a a first temperature lower than a SiO2 viscoelastic temperature, and the silicon substrate 22 is subjected to an oxidizing atmosphere at the first temperature and for a first time period and a second step where a second oxide portion 32 is grown between the first oxide portion and the silicon substrate by exposing the substrate 22 to an oxidizing atmosphere at a second temperature higher than the SiO2 viscoelastic temperature and for a second time period. The second oxide portion 32 may have a thickness in a range of about 25 to 50% of a total thickness of the graded oxide layer.

    Gate oxides
    2.
    发明专利
    Gate oxides 未知

    公开(公告)号：GB2355852A

    公开(公告)日：2001-05-02

    申请号：GB0015503

    申请日：2000-06-23

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： CHEN YUANNING ,  CHETLUR SUNDAR SRINIVASAN ,  MERCHANT SAILESH MANSINH ,  ROY PRADIP KUMAR

    IPC: C30B33/00 ,  H01L21/28 ,  H01L21/316 ,  H01L29/51

    Abstract: A gate oxide is fabricated in a multi stage process in which an oxide layer is formed initially at a first temperature below the viscoelastic temperature of silicon oxide, and subsequently at a second high temperature above the viscoelastic temperature of silicon oxide. This process provides an oxide film comprising first and second portions 31,32, where the first silicon oxide portion 31 comprises between 25-98% of the total oxide thickness, and the second oxide portion 32 is more amorphous and more dense than the first portion. The ultrathin gate oxides (less than 2.5nm) have low interface trap density (less than 5x10 10 cm 2 ), low stress (less than 2x10 9 dynes/cm 2 ), and low defect densities (less than 0.1 defects / cm 2 ).

    Gate oxide fabrication process
    8.
    发明专利
    Gate oxide fabrication process 未知

    公开(公告)号：GB2367427A8

    公开(公告)日：2002-08-02

    申请号：GB0118143

    申请日：2000-01-12

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： CHEN YUANNING ,  CHETLUR SUNDAR SRINIVASAN ,  ROY PRADIP KUMAR

    IPC: C30B33/00 ,  H01L21/28 ,  H01L21/283 ,  H01L21/316 ,  H01L21/318 ,  H01L29/51 ,  H01L29/78

    Abstract: A method for making an oxide layer on a silicon substrate produces an oxide layer including graded portions with greatly reduced stress. The method includes growing a first oxide portion over a substrate by upwardly ramping the substrate to a first temperature lower than a SiO2 viscoelastic temperature. Thereafter a second oxide portion is grown between the first oxide portion and the silicon substrate by exposing the silicon substrate to an oxidizing ambient at a second temperature higher than the SiO2 viscoelastic temperature. The second oxide portion may have a thickness in a range of about 25 to 50% of a total thickness of the graded oxide layer.

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