公开(公告)号：JP2001291684A

公开(公告)日：2001-10-19

申请号：JP2001053530

申请日：2001-02-28

Applicant: LUCENT TECHNOLOGIES INC

Inventor： MERCHANT SAILESH M ,  SUDAANSHU MISURA ,  ROY PRADIP K

IPC: B24B37/00 ,  C09G1/02 ,  C09K3/14 ,  H01L21/304 ,  H01L21/321

Abstract: PROBLEM TO BE SOLVED: To provide a high-speed, highly accurate polishing method. SOLUTION: The chemical mechanical polishing composition comprises multiple abrasive particles, triazole or a derivative thereof of in a quantity which is effective for corrosion proof property, ferricyanide salt oxidizing agent of such a quantity as effective for oxidation, and water, and has a pH range of 1-6. The polishing method for polishing a metallization layer on a semiconductor wafer comprises a step for removing at least a part of the metallization layer by polishing it, using that composition.

公开(公告)号：JP2000294746A

公开(公告)日：2000-10-20

申请号：JP2000004788

申请日：2000-01-13

Applicant: LUCENT TECHNOLOGIES INC

Inventor： FRITZINGER LARRY BRUCE ,  LAYADI NACE ,  MERCHANT SAILESH M ,  ROY PRADIP K

IPC: H01L21/8242 ,  H01L21/02 ,  H01L21/285 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To obtain a compact capacitor that solves a problem regarding a leakage current or other problems. SOLUTION: The capacitor for an integrated circuit is composed of a conductive plug 7 with an upper surface and an exposed sidewall, and an electrode layer 9 formed on the sidewall of the conductive plug 7. Then, the above side wall includes a layer 3 or 5 made of a material selected form a group consisting of titanium(Ti) and titanium nitride(TiN), and the material of the electrode layer 8 contains neither titanium(Ti) not the titanium nitride(TiN).

公开(公告)号：JP2001298005A

公开(公告)日：2001-10-26

申请号：JP2001058124

申请日：2001-03-02

Applicant: LUCENT TECHNOLOGIES INC

Inventor： SADOHANSHU MISURA ,  MERCHANT SAILESH MANSINH ,  ROY PRADIP K

IPC: B24B37/04 ,  C09G1/02 ,  C09K3/14 ,  H01L21/304 ,  H01L21/3205 ,  B24B37/00

Abstract: PROBLEM TO BE SOLVED: To provide a method by which a residual released material can be removed in such a way that pad adjustment is not required after chemical mechanical polishing. SOLUTION: This method for polishing the surface of an integrated circuit comprises a step of feeding colloidal slurry (6) having released particles containing a magnesium compound onto the surface of the integrated circuit, a step of polishing the surface by means of a polishing device, and a step of cleaning the surface with a solvent which reacts with the magnesium compound. In the cleaning step, the particles produced as a result of the polishing and the colloidal slurry are removed by forming a water-soluble salt through the reaction.

公开(公告)号：JP2000208430A

公开(公告)日：2000-07-28

申请号：JP2000006222

申请日：2000-01-12

Applicant: LUCENT TECHNOLOGIES INC

Inventor： SANDER SRINIVASAN CHETTLER ,  AISHIKKU C KIZURIYARI ,  MICHAEL A LARRY ,  MA YI ,  ALAN R MASSENGEERU ,  ROY PRADIP K

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/336

Abstract: PROBLEM TO BE SOLVED: To reduce hot carrier injection and deterioration by incorporating nitrogen of high concentration in an interface between a lightly doped drain structure and a gate oxide. SOLUTION: Lightly doped drain structures 36, 38 are formed by a first doping in source and drain regions 28, 30. After a spacer 40 is formed in a vertical sidewall 22 of a gate conductor region, source and drain injection matters 42, 44 which are deeper and wider than the lightly doped drain structures 36, 38 and whose dopant concentration is further high are formed in the source and drain regions 28, 30. The drain region 30 is annealed in atmosphere of at least one kind of nitrogen oxide, ammonia and dinitrogen monoxide. Thereby, nitrogen of high concentration can be incorporated in silicon/silicon dioxide interface between a gate oxide 24 and the lightly doped drain structure 38.

公开(公告)号：JPH11265887A

公开(公告)日：1999-09-28

申请号：JP33314998

申请日：1998-11-24

Applicant: LUCENT TECHNOLOGIES INC

Inventor： MA YI ,  MERCHANT SAILESH M ,  ROY PRADIP K

IPC: H01L21/28 ,  H01L21/314 ,  H01L21/318 ,  H01L21/32 ,  H01L21/762 ,  H01L29/51

Abstract: PROBLEM TO BE SOLVED: To enable a nitride layer to be released from its inner stress and set uniform in thickness by a method wherein a first sub-layer and a second sub-layer are deposited at different deposition rates, and this deposition process is repeatedly carried out a prescribed number of times to make the nitride layer as thick as required. SOLUTION: A nitride layer 16 is varied in deposition rate with time, a sequence of deposition starts at a low deposition rate and then transfers to a high deposition rate, and this deposition process is carried at deposition rates which are cyclically changed. A gate oxide structure comprises a first oxide layer 14, the nitride layer 16, and a second oxide layer 18. A deposition rate difference can be realized by changing, for instance, a pressure or a gas flow rate or both of them at the same time. For instance, a deposition process of low deposition rate is carried out at a temperature of 750 to 800 deg.C, and a deposition process of high deposition rate is carried out at a temperature of 800 to 850 deg.C. During a deposition term, these changes in deposition rate make deposited nitride serve as sub-layers. Interfaces between the sub-layers function as stress relaxation mechanisms in the gate oxide structure, whereby the multilayered nitride layer 16 is improved in uniformity, and pinholes and micro cracks present in the nitride films are lessened in number.

公开(公告)号：JPH1174265A

公开(公告)日：1999-03-16

申请号：JP16977498

申请日：1998-06-17

Applicant: LUCENT TECHNOLOGIES INC

Inventor： BRADY DAVID C ,  KIZILYALLI ISIK C ,  ROY PRADIP K ,  VAIDYA HEM M

IPC: H01L21/316 ,  H01L21/318 ,  H01L21/32 ,  H01L21/76

Abstract: PROBLEM TO BE SOLVED: To prevent lifting phenomenon of a laminate of a semiconductor structure, especially with a pad oxide layer by constituting an insulative structured body of a uniform thickness by forming a first laminated sub-layer at a first deposit speed and a second laminated sub-layer at a second deposit speed on a substrate one by one. SOLUTION: A first laminated sub-layer is formed at a first deposit speed and a second laminated sub-layer is formed at a second deposit speed on a substrate, constituting an insulation structure body of a uniform thickness. The first deposit speed in the range of 0.5 to 1 nm/minute is desirable, and the second deposit velocity in the range of 3 to 5 nm/minute is desirable. Move specifically, a field oxide 20 is insulated and formed between insulation structure bodies 16 on a semiconductor wafer 10. The thin field oxide 20 of about 150 to 250 nm reduces a length of bird's beak and reduces relief phenomenon of a lamination body. A stress inside the insulation structure body 16 is reduced since the lifting phenomenon is reduced.

公开(公告)号：JP2001189290A

公开(公告)日：2001-07-10

申请号：JP2000307040

申请日：2000-10-06

Applicant: LUCENT TECHNOLOGIES INC

Inventor： MISRA SUDHANSHU ,  MERCHANT SAILESH MANSINH ,  ROY PRADIP K

IPC: B24B37/00 ,  C09G1/02 ,  C09K3/14 ,  C09K13/00 ,  H01L21/304 ,  H01L21/306 ,  H01L21/321

Abstract: PROBLEM TO BE SOLVED: To provide a novel CMP slurry, in which metal particles are removed to avoid damaging and/or contaminating a semiconductor wafer. SOLUTION: The CM slurry includes a first emulsion, having a continuous aqueous phase and a second emulsion. The first emulsion includes abrasive particles, and the second emulsion captures metal particles polished from the semiconductor wafer. Thus, the metal particles can be removed from the slurry during CMP to avoid damaging and/or contaminating the semiconductor wafer.

公开(公告)号：JP2001189287A

公开(公告)日：2001-07-10

申请号：JP2000317404

申请日：2000-10-18

Applicant: LUCENT TECHNOLOGIES INC

Inventor： MERCHANT SAILESH MANSINH ,  ROY PRADIP K

IPC: H01L21/288 ,  H01L21/28 ,  H01L21/768 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To provide a method for controlling a copper microstructure, to provide a uniform copper microstructure which hardly deteriorates greatly during self annealing or the following processing steps. SOLUTION: In this integrated circuit device provided with copper interconnects 18, 20 and 22, the copper interconnect has alloying elements therein, which prevent grain growth of the copper due to self annealing. The alloying elements comprise at least one of the group of Cr, Co, Zn, and Ag.

公开(公告)号：JP2000232208A

公开(公告)日：2000-08-22

申请号：JP35361599

申请日：1999-12-13

Applicant: LUCENT TECHNOLOGIES INC

Inventor： KIZILYALLI ISIK C ,  MERCHANT SAILESH MANSINH ,  ROY PRADIP K ,  WONG YIU-HUEN

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/285 ,  H01L21/82 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To add a buried memory to a capacitor without making a sharp change to the manufacturing process of the capacitor by a method wherein in the case where the dielectric layer of the capacitor is formed of a tantalum pentaoxide (Ta2O5) layer, a diffused barrier layer formed of a tungsten nitride(WN) layer instead of a titanium nitride(TiN) layer is provided in the capacitor. SOLUTION: A transistor structure 205 and an interconnected part 210 coming into contact with a capacitor 215 are shown as parts of a buried memory cell structure 200. The capacitor 215 has a first (bottom) electrode comprising a conductive layer 220 for adhesion, a barrier layer 225, which is formed on the interconnected part 210 and consists of a tungsten nitride layer or a tungsten silicon nitride layer, and a dielectric layer 230 and a titanium layer on the first electrode, a second electrode 240 on the layer 230 and a layer 235, which is used as a selective matter, reduce the layer 230. A first layer on the interconnected region is made of the titanium layer and the material for the layer 225 is the tungsten nitride(WN) layer, the tungsten silicon nitride(WSiN) layer or a combination of the tungsten nitride(WN) layer to the tungsten silicon nitride(WSiN) layer.

公开(公告)号：JP2000208743A

公开(公告)日：2000-07-28

申请号：JP2000006223

申请日：2000-01-12

Applicant: LUCENT TECHNOLOGIES INC

Inventor： ALERS GLENN B ,  SEINGUMUU CHOI ,  MERCHANT SAILESH M ,  ROY PRADIP K

IPC: H01G13/00 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a high dielectric constant and quality with less insulation leakage so that reduction of an insulating layer by the metal of an electrode is prevented, by allowing a capacitor to comprise a substantially flat upper side surface, so formed as to be substantially the same plane as adjoining upper side surface part of an insulating layer. SOLUTION: An electrolytic capacitor 24 comprises a substantially flat upper side surface, so formed as to be substantially the same plane with the upper side surface part of an adjoining third insulating (dielectric) layer 42. The end of a lower side metal electrode 44 and that of a capacitor insulating (dielectric) layer 46 are terminated at the upper side surface of a capacitor. The capacitor insulating layer 46 has a permittivity almost equal to 25 or above which attains a desired capacitor characteristics. An upper side electrode comprises a conductive metal layer 48 and a conductive metal layer 50. The conductive metal layer 48 functions as a barrier layer as well, preventing a metal from the metal conductive layer 50, for example, copper from diffusing in the insulating layer 46.