公开(公告)号：JP2001237323A

公开(公告)日：2001-08-31

申请号：JP2001009599

申请日：2001-01-18

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DONALD THOMAS QUINER ,  MISRA SUDHANSHU ,  DENNIS OKUMU OUMA ,  SAXENA VIVEK ,  JOHN MITCHELL SHARP

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/82 ,  H01L23/528 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To perform planarization easily during manufacture of a semiconductor device and minimize a parasitic capacitance with an adjacent wiring structure. SOLUTION: This is a method for forming a layout for a wiring layer of a semiconductor device to perform uniform planarization easily during manufacture of the semiconductor device. The method includes a step of determining an active wiring structure density of each of a plurality of layout regions in a wiring layout. The method further includes a step of adding a dummy filling structure to each layout region to obtain desired densities of the active wiring structure and the dummy filling structure so that uniform planarization during manufacture of the semiconductor device can be performed easily. Since the dummy filling structure is added to obtain desired densities of the active wiring structure and the dummy filling structure, the dummy filling structure is not added unnecessarily and each layout region has a uniform density.