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    MUTUAL CONNECTION LAYER AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING THE LAYER
    1.
    发明专利
    MUTUAL CONNECTION LAYER AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING THE LAYER 失效

    公开(公告)号：JP2001237323A

    公开(公告)日：2001-08-31

    申请号：JP2001009599

    申请日：2001-01-18

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： DONALD THOMAS QUINER ,  MISRA SUDHANSHU ,  DENNIS OKUMU OUMA ,  SAXENA VIVEK ,  JOHN MITCHELL SHARP

    IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/82 ,  H01L23/528 ,  H01L27/04

    Abstract: PROBLEM TO BE SOLVED: To perform planarization easily during manufacture of a semiconductor device and minimize a parasitic capacitance with an adjacent wiring structure. SOLUTION: This is a method for forming a layout for a wiring layer of a semiconductor device to perform uniform planarization easily during manufacture of the semiconductor device. The method includes a step of determining an active wiring structure density of each of a plurality of layout regions in a wiring layout. The method further includes a step of adding a dummy filling structure to each layout region to obtain desired densities of the active wiring structure and the dummy filling structure so that uniform planarization during manufacture of the semiconductor device can be performed easily. Since the dummy filling structure is added to obtain desired densities of the active wiring structure and the dummy filling structure, the dummy filling structure is not added unnecessarily and each layout region has a uniform density.

    Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics
    3.
    发明专利
    Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics 未知

    公开(公告)号：GB2359661A

    公开(公告)日：2001-08-29

    申请号：GB0019483

    申请日：2000-08-08

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： ABDELGADIR MAHJOUB ALI ,  LAYADI NACE ,  MERCHANT SAILESH MANSINH ,  SAXENA VIVEK ,  YIH PEI H

    IPC: H01L21/3205 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: A cap or barrier that can prevent the migration of impurities in low dielectric constant material, thereby preventing the impurities from attacking conductive elements in subsequent levels of a multi-level integrated circuit structure. The integrated circuit may be fabricated by disposing the diffusion-preventing barrier layer (104) between a first dielectric layer (103) and the conductive layer (201) at an upper level of the integrated circuit. The diffusion preventing barrier layer may be formed in-situ over the impurity containing dielectric material with the subsequent disposition of a metal layer thereover, and further processing of a multi-layer dielectric structure to include polishing. The in-situ deposition of the cap or barrier layer prevents the exposure of the impurity containing layer to atmosphere, thereby avoiding contamination of the layer by moisture absorption, hydrogen absorption, or the like. In an exemplary embodiment, the diffusion preventing barrier layer is a material containing silicon oxide or silicon rich silicon oxide SiO x , where x is preferably less than 2 and the first dielectric layer is fluorosilicate glass (FSG).

    Method for making an interconnect layout and a semiconductor device including an interconnect layout
    5.
    发明专利
    Method for making an interconnect layout and a semiconductor device including an interconnect layout 未知

    公开(公告)号：GB2364598A

    公开(公告)日：2002-01-30

    申请号：GB0100169

    申请日：2001-01-04

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： CWYNAR DONALD THOMAS ,  MISRA SUDHANSHU ,  OUMA DENNIS OKUMU ,  SAXENA VIVEK ,  SHARPE JOHN MICHAEL

    IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/82 ,  H01L23/528 ,  H01L27/04 ,  H01L21/02

    Abstract: A method for making a layout for an interconnect layer of a semiconductor device to facilitate uniformity of planarization during manufacture of the semiconductor device includes determining an active interconnect feature density for each of a plurality of layout regions 60(1)-60(n) of the interconnect layout (30, Figure 5). The method further includes adding dummy fill features 74(1)-74(n) to the layout region to obtain a desired density of active interconnect features 70(1)-70(n) and dummy fill features 74(1)-74(n) to facilitate uniformity of planarization during the manufacturing of the semiconductor device. The positions of the dummy film features 74(1)-74(n) may be based upon capacitance with adjacent active interconnect features, or with capacitance with adjacent active interconnect features in an adjacent interconnect layer. The dummy fill features 74(1)-74(n) may have a minimum dummy fill feature lateral dimension based upon a dielectric layer deposition bias for a dielectric layer deposited over the interconnect layer. A semiconductor device has a substrate and at least one interconnect layer overlying the semiconductor substrate comprising a plurality of layout regions. Each layout region 60(1)-60(n) comprises an active interconnect feature region and a dummy fill feature region adjacent thereto for facilitating uniformity of planarization during manufacture the semiconductor device. Each of the dummy fill regions has a different density with respect to other dummy fill regions so that a combined density of the active interconnect feature region and the dummy fill feature region for a respective layout region is substantially uniform with respect to the combined density of other layer regions. The density of the active interconnect features for a respective layout region may be determined using a layout algorithm.

    Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics
    6.
    发明专利
    Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics 未知

    公开(公告)号：GB2359661B

    公开(公告)日：2002-11-20

    申请号：GB0019483

    申请日：2000-08-08

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： ABDELGADIR MAHJOUB ALI ,  LAYADI NACE ,  MERCHANT SAILESH MANSINH ,  SAXENA VIVEK ,  YIH PEI H

    IPC: H01L21/3205 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: A cap or barrier layer that can prevent the migration of impurities in low dielectric constant material, thereby preventing the impurities from attacking conductive elements in subsequent levels of a multi-level integrated circuit structure. The integrated circuit by may be fabricated by disposing the diffusion-preventing barrier layer between a first dielectric layer and the conductive layer at an upper level of the integrated circuit. The diffusion preventing barrier layer may be formed in-situ over the impurity containing dielectric material with the subsequent disposition of a metal layer thereover, and further processing of a multi-layer dielectric structure to include polishing. The in-situ deposition of the cap or barrier layer prevents the exposure of the impurity containing layer to atmosphere, thereby avoiding contamination of the layer by moisture absorption, hydrogen absorption, or the like. In an exemplary embodiment, the diffusion preventing barrier layer is a material containing silicon oxide or silicon rich silicon oxide SiOx, where x is preferably less than 2.

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