公开(公告)号：JP2001057385A

公开(公告)日：2001-02-27

申请号：JP2000189019

申请日：2000-06-23

Applicant: LUCENT TECHNOLOGIES INC

Inventor： MERCHANT SAILESH MANSINH ,  MISRA SUDHANSHU

IPC: C23C16/40 ,  H01L21/28 ,  H01L21/304 ,  H01L21/306 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To passivate a surface on an interconnection part by a method wherein the interconnection parts made of copper just deposited electrically are exposed to any alkoxide vapor of W or Cr at high temperature. SOLUTION: A semiconductor wafer 35 formed by an etching process has a first oxide layer 36 and a trench 34, and this trench 34 is filled up with copper to form an interconnection part. Vapor 44 is injected from the upside into a MOCVD reactor 40 having a semiconductor wafer 30 disposed on a check 42, and an exhaust 46 is made from the lowerside. An interconnection part 22 made of exposed copper just deposited electrically is exposed to alkoxide vapor of W or Cr at high temperatures, and a passivation layer 50 of copper tungstate and copper chromate as a passivation surface on the copper interconnection part is formed. After that, a chemical machine polishing is performed on a semiconductor wafer 30. Next, a standard process is carried out with respect to a wafer. Copper is corroded, and for this reason, a passivation process is necessary.

公开(公告)号：JP2001237323A

公开(公告)日：2001-08-31

申请号：JP2001009599

申请日：2001-01-18

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DONALD THOMAS QUINER ,  MISRA SUDHANSHU ,  DENNIS OKUMU OUMA ,  SAXENA VIVEK ,  JOHN MITCHELL SHARP

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/82 ,  H01L23/528 ,  H01L27/04

Abstract: PROBLEM TO BE SOLVED: To perform planarization easily during manufacture of a semiconductor device and minimize a parasitic capacitance with an adjacent wiring structure. SOLUTION: This is a method for forming a layout for a wiring layer of a semiconductor device to perform uniform planarization easily during manufacture of the semiconductor device. The method includes a step of determining an active wiring structure density of each of a plurality of layout regions in a wiring layout. The method further includes a step of adding a dummy filling structure to each layout region to obtain desired densities of the active wiring structure and the dummy filling structure so that uniform planarization during manufacture of the semiconductor device can be performed easily. Since the dummy filling structure is added to obtain desired densities of the active wiring structure and the dummy filling structure, the dummy filling structure is not added unnecessarily and each layout region has a uniform density.

公开(公告)号：JP2001189290A

公开(公告)日：2001-07-10

申请号：JP2000307040

申请日：2000-10-06

Applicant: LUCENT TECHNOLOGIES INC

Inventor： MISRA SUDHANSHU ,  MERCHANT SAILESH MANSINH ,  ROY PRADIP K

IPC: B24B37/00 ,  C09G1/02 ,  C09K3/14 ,  C09K13/00 ,  H01L21/304 ,  H01L21/306 ,  H01L21/321

Abstract: PROBLEM TO BE SOLVED: To provide a novel CMP slurry, in which metal particles are removed to avoid damaging and/or contaminating a semiconductor wafer. SOLUTION: The CM slurry includes a first emulsion, having a continuous aqueous phase and a second emulsion. The first emulsion includes abrasive particles, and the second emulsion captures metal particles polished from the semiconductor wafer. Thus, the metal particles can be removed from the slurry during CMP to avoid damaging and/or contaminating the semiconductor wafer.

公开(公告)号：GB2364598A

公开(公告)日：2002-01-30

申请号：GB0100169

申请日：2001-01-04

Applicant: LUCENT TECHNOLOGIES INC

Inventor： CWYNAR DONALD THOMAS ,  MISRA SUDHANSHU ,  OUMA DENNIS OKUMU ,  SAXENA VIVEK ,  SHARPE JOHN MICHAEL

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/82 ,  H01L23/528 ,  H01L27/04 ,  H01L21/02

Abstract: A method for making a layout for an interconnect layer of a semiconductor device to facilitate uniformity of planarization during manufacture of the semiconductor device includes determining an active interconnect feature density for each of a plurality of layout regions 60(1)-60(n) of the interconnect layout (30, Figure 5). The method further includes adding dummy fill features 74(1)-74(n) to the layout region to obtain a desired density of active interconnect features 70(1)-70(n) and dummy fill features 74(1)-74(n) to facilitate uniformity of planarization during the manufacturing of the semiconductor device. The positions of the dummy film features 74(1)-74(n) may be based upon capacitance with adjacent active interconnect features, or with capacitance with adjacent active interconnect features in an adjacent interconnect layer. The dummy fill features 74(1)-74(n) may have a minimum dummy fill feature lateral dimension based upon a dielectric layer deposition bias for a dielectric layer deposited over the interconnect layer. A semiconductor device has a substrate and at least one interconnect layer overlying the semiconductor substrate comprising a plurality of layout regions. Each layout region 60(1)-60(n) comprises an active interconnect feature region and a dummy fill feature region adjacent thereto for facilitating uniformity of planarization during manufacture the semiconductor device. Each of the dummy fill regions has a different density with respect to other dummy fill regions so that a combined density of the active interconnect feature region and the dummy fill feature region for a respective layout region is substantially uniform with respect to the combined density of other layer regions. The density of the active interconnect features for a respective layout region may be determined using a layout algorithm.