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    CLUSTER PACKAGING OF IC CHIP FOR MULTI-CHIP PACKAGE
    1.
    发明专利
    CLUSTER PACKAGING OF IC CHIP FOR MULTI-CHIP PACKAGE 失效

    公开(公告)号：JP2001203315A

    公开(公告)日：2001-07-27

    申请号：JP2000362327

    申请日：2000-11-29

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： GABARA THADDEUS JOHN ,  JERICHIO J JAKARA ,  O'CONNOR KEVIN JOHN ,  TAI KING L

    IPC: H01L21/66 ,  H01L25/04 ,  H01L25/18

    Abstract: PROBLEM TO BE SOLVED: To provide a single integrated cluster chip having a plurality of chip sites packaged in an IC package of a maltichip module-(MCM). SOLUTION: A fully functioning cluster of chip sites or an almost fully functioning chip sites is identified by a wafer level test. The cluster is individualized as a single chip, and packaged. One cluster may contain, for example, a combination of chip types such as a combination of memories and logic circuits. The cluster normally includes 3 to 25 pieces of chip sites. Two or more types of clusters can be identified and created on a single wafer. The remaining fully functioning chips are individualized as individual chips, and can be packaged as a single chip package or in any of the MCM by a conventional method. Mutually connected substrates are added with an arrangement configuration of silicon-on-silicon to the cluster, and a plurality of chip sites can be connected to each other.

    INTEGRATED CIRCUIT PACKAGE
    2.
    发明专利
    INTEGRATED CIRCUIT PACKAGE 审中-公开

    公开(公告)号：JP2003110087A

    公开(公告)日：2003-04-11

    申请号：JP2002231207

    申请日：2002-08-08

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： FRYE ROBERT CHARLES ,  LOW YEE LENG ,  O'CONNOR KEVIN JOHN

    IPC: H01L25/18 ,  H01L23/522 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07

    Abstract: PROBLEM TO BE SOLVED: To provide a multilevel mutual connection assembly of low cost whose structure is simple. SOLUTION: At least a part of an interchip mutual connection circuit is shifted to a smaller (upper part) chip. When a plurality of upper part chips exist, an interchip circuit is designed as if mutual connection circuits on two chips contain a common mutual connection level, i.e., in such a manner that mutual connection to one chip out of upper chips contains a runner on another upper chip. The feature of constitution of this invention is that a gap which has been existed in chip-on-chip bonding is used for providing air insulation type crossover connection.

    MEMORY CELL WITH PLANE-LIKE ACCESS LINE
    3.
    发明专利
    MEMORY CELL WITH PLANE-LIKE ACCESS LINE 失效

    公开(公告)号：JP2000236029A

    公开(公告)日：2000-08-29

    申请号：JP2000029413

    申请日：2000-02-07

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： O'CONNOR KEVIN JOHN

    IPC: G11C11/41 ,  G11C7/12 ,  G11C7/18 ,  G11C8/14 ,  G11C11/413 ,  G11C11/418 ,  G11C11/419 ,  H01L21/3205 ,  H01L21/8244 ,  H01L23/52 ,  H01L27/11

    Abstract: PROBLEM TO BE SOLVED: To reduce capacitive coupling between access lines by sealing a bit line by a runner of a fixed voltage and connecting the runner to a ground voltage or a power supply voltage through mutual connection between levels. SOLUTION: A shield runner is applied between bit lines which are most susceptible to capacitive coupling and the shield runner is maintained at a fixed potential (such as VDD or VSS). An applied bit line shield 51 functions as a shield between a second read bit line 22 and a first write bit line 18, and another bit line shield 53 functions as a shield between a first read bit line 19 and a second write bit line 21. Therefore, no extra treatment step is required for forming the shield runners 51, 53. The shield runners 51, 53 can be interconnected between VDD or VSS levels by a contact pad 55.

    INTEGRATED CIRCUIT PACKAGE
    4.
    发明专利
    INTEGRATED CIRCUIT PACKAGE 失效

    公开(公告)号：JPH11195746A

    公开(公告)日：1999-07-21

    申请号：JP28571498

    申请日：1998-10-07

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： FRYE ROBERT CHARLES ,  LOW YEE LENG ,  O'CONNOR KEVIN JOHN

    IPC: H01L25/18 ,  H01L23/522 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07

    Abstract: PROBLEM TO BE SOLVED: To assemble an inexpensive multi-level mutual connection with a simple structure by shifting at lest a part of an inter-chip mutual connecting circuit to a more smaller upper chip and including a runner on the other upper chip in the mutual connection to one of the upper chips. SOLUTION: A metal layer at a certain level is formed on a support chip. An upper chip 41 has a contact-point pad 62. A mutual connecting circuit at the single level is indicated by runners 63-65. An upper chip 67 undergoes flip- chip connection to a support-chip substrate 61 with solder bumps 68 and 69. An under-bump metablized layer 71 is ranged between the solder bump and the chip surface. In the metallic mutually connecting structure at the single level, runners 72-74 are formed on the upper chip 67. The runner 73 on the surface of the upper chip crosses the runner 64 on the surface of the support chip supported by the solder bumps 68 and 69. This cross-over is insulated with air by a gap 75.

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