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1.发明专利
公开(公告)号：JP2001230682A
公开(公告)日：2001-08-24
申请号：JP2000389807
申请日：2000-12-22
Applicant: LUCENT TECHNOLOGIES INC
Inventor： AZADET KAMERAN , HARATSCH ERICH FRANZ
Abstract: PROBLEM TO BE SOLVED: To provide a method and a device for improving processing time of sequence estimation technology, such as reduced-state sequence estimation(RSSE) which reduces complexity. SOLUTION: By previously calculating a possible value for the branch metrics in RSSE, pipelining and critical path shortening are enabled. By calculating branch metrics concerning the combination of all symbols possible for a channel memory in advance, a branch metrics unit(BMU) and a decision feedback unit(DFU) can be removed from a feedback loop, so that the critical paths can be reduced. A look-ahead branch metrics unit(LABMU) and an inter-symbol interference canceler(ISIC) previously calculate branch metrics, corresponding to all values possible for the channel memory.
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Patent Agency Ranking
公开(公告)号：JP2001036437A
公开(公告)日：2001-02-09
申请号：JP2000166158
申请日：2000-06-02
Applicant: LUCENT TECHNOLOGIES INC
Inventor： HARATSCH ERICH FRANZ , HARISH BISUWANASAN
Abstract: PROBLEM TO BE SOLVED: To reduce the complicity of the hardware of an RSSE method with respect to the prescribed number of states and to reduce the problem of a critical path by processing a low-order tail tap with the algorithm of low complicity such as a DFE method and processing only a high-order initial tap by the RSSE method. SOLUTION: A receiver 200 contains a temporary decision/tail processing circuit 400, processes a low-order tail tap with the cancellation algorithm of low complicity such as a decision feedback equalizer (EDF) method and cancels the tail tap by using temporary decision. The receiver 200 contains an RSSE circuit 500 as well and processes only an initial tap by a reduced state sequence (RSSE) method. Inter-symbol interference associated with the tail tap is removed by the DFE method first and the RSSE method is applied only to the more important tail tap. Namely, the taps 1 to U are processed by using RSSE and the taps U+1 to L are processed by DFE.
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公开(公告)号：AU7237100A
公开(公告)日：2001-06-28
申请号：AU7237100
申请日：2000-12-19
Applicant: LUCENT TECHNOLOGIES INC
Inventor： AZADET KAMERAN , HARATSCH ERICH FRANZ
Abstract: A method and apparatus are disclosed for improving the processing time of reduced complexity sequence estimation techniques, such as reduced state sequence estimation (RSSE). The possible values for the branch metrics in the RSSE are precomputed to permit pipelining and the shortening of the critical path. Precomputing the branch metrics for all possible symbol combinations in the channel memory makes it possible to remove the branch metrics unit (BMU) and decision-feedback unit (DFU) from the feedback loop, thereby reducing the critical path. A look-ahead branch metrics unit (LABMU) and an intersymbol interference canceller (ISIC) precompute the branch metrics for all possible values for the channel memory. At the beginning of each decoding cycle, a set of multiplexers (MUXs) select the appropriate branch metrics based on the survivor symbols in the corresponding survivor path cells (SPCs), which are then sent to an add-compare-select unit (ACSU). The computational load of the precomputations is reduced for multi-dimensional trellis codes by precomputing each dimension of the multi-dimensional trellis code separately. Prefiltering techniques are used to reduce the computational complexity by shortening the channel memory. A hybrid survivor memory architecture is also disclosed for a RSSE for a channel having a channel memory of length L, where the survivors corresponding to the L past decoding cycles are stored in a register exchange architecture (REA), and survivors corresponding to later decoding cycles are stored in a trace-back architecture (TBA) or register exchange architecture (REA). Symbols are mapped to information bits to reduce the word size before being moved from the first register exchange architecture (REA) to the trace-back architecture (TBA) or the second register exchange architecture (REA).
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公开(公告)号：CA2327910A1
公开(公告)日：2001-06-23
申请号：CA2327910
申请日：2000-12-08
Applicant: LUCENT TECHNOLOGIES INC
Inventor： HARATSCH ERICH FRANZ , AZADET KAMERAN
Abstract: A method and apparatus are disclosed for improving the processing time of reduced complexity sequence estimation techniques, such as reduced state sequence estimation (RSSE). The possible values for the branch metrics in the RSSE ar e precomputed to permit pipelining and the shortening of the critical path. Precomputing the branch metrics for all possible symbol combinations in the channel memor y makes it possible to remove the branch metrics unit (BMU) and decision-feedback unit (DFU) from the feedback loop, thereby reducing the critical path. A look-ahead branch metrics unit (LABMU) and an intersymbol interference canceller (ISIC) precompute the branch metrics for all possible values for the channel memory. At the beginning of each decoding cycle, a set of multiplexers (MUXs) select the appropriate branch metrics based on the survivor symbols in the corresponding survivor path cells (SPCs ), which are then sent to an add-compare-select unit (ACSU). The computational load of th e precomputations is reduced for multi-dimensional trellis codes by precomputi ng each dimension of the multi-dimensional trellis code separately. Prefiltering techniques are used to reduce the computational complexity by shortening the channel memory . A hybrid survivor memory architecture is also disclosed for a RSSEfor a channe l having a channel memory of length L, where the survivors corresponding to the L past decoding cycles are stored in a register exchange architecture (REA), and survivors corresponding to later decoding cycles are stored in a trace-back architecture (TBA) or register exchange architecture (REA). Symbols are mapped to information bits to reduc e the word size before being moved from the first register exchange architecture (REA) to the trace-back architecture (TBA) or the second register exchange architecture (REA).
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公开(公告)号：CA2310178C
公开(公告)日：2005-08-30
申请号：CA2310178
申请日：2000-05-29
Applicant: LUCENT TECHNOLOGIES INC
Inventor： VISWANATHAN HARISH , HARATSCH ERICH FRANZ
Abstract: A method and apparatus are disclosed for reducing the complexity of reduced state sequence estimation (RSSE) techniques for a given number of states while also reducing the critical path problem. The signal energy of a pulse that h as gone through a minimum-phase channel is concentrated in the initial taps. A communications channel is represented using a discrete time model, where the channel impuls e response has a memory length, L, denoted by {.function.'k}~=o, where .function.k is t he coefficient for channel tap k. Taps one through U are referred to as the initial taps, and taps U+1 through L are referred to as the tail taps, where U is a prescribed number. The less significant tail taps are processed with a lower complexity cancellation algorithm, such as a decision-feedback equalizer (DFE) technique, that cancels the tail taps using tentative decisions. Thereafter, only the more significant initial taps are processed with a reduced state sequence estimation (RSSE) technique. The DFE technique initially removes th e intersymbol interference associated with the tail taps, then the RSSE technique (or M- algorithm (MA)) is applied only to the more important tail taps. Taps one through U are processed using the RSSE technique and taps U+1 through L are processed with the lower complexity decision-feedback equalizer (DFE). A receiver is disclosed that includes a tentative decision/tail processing circuit, such as a decision- feedback equalizer (DFE) technique, for processing the less significant tail taps and an RSSE circuit for processing the initial taps.
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公开(公告)号：CA2310178A1
公开(公告)日：2000-12-04
申请号：CA2310178
申请日：2000-05-29
Applicant: LUCENT TECHNOLOGIES INC
Inventor： VISWANATHAN HARISH , HARATSCH ERICH FRANZ
Abstract: A method and apparatus are disclosed for reducing the complexity of reduced state sequence estimation (RSSE) techniques for a given number of states while also reducing the critical path problem. The signal energy of a pulse that has gone through a minimum-phase channel is concentrated in the initial taps. A communications channel is represented using a discrete time model, where the channel impulse response has a memory length, L, denoted by {f k }~=o, where f k is the coefficient for channel tap k. Taps one through U are referred to as the initial taps, and taps U+1 through L are referred to as the tail taps, where U is a prescribed number. The less significant tail taps are processed with a lower complexity cancellation algorithm, such as a decision-feedback equalizer (DFE) technique, that cancels the tail taps using tentative decisions. Thereafter, only the more significant initial taps are processed with a reduced state sequence estimation (RSSE) technique. The DFE technique initially removes the intersymbol interference associated with the tail taps, then the RSSE technique (or M-algorithm (MA)) is applied only to the more important tail taps. Taps one through U are processed using the RSSE technique and taps U+1 through L are processed with the lower complexity decision-feedback equalizer (DFE). A receiver is disclosed that includes a tentative decision/tail processing circuit, such as a decisionfeedback equalizer (DFE) technique, for processing the less significant tail taps and an RSSE circuit for processing the initial taps.
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