公开(公告)号：GB2350929A

公开(公告)日：2000-12-13

申请号：GB0009611

申请日：2000-04-18

Applicant: LUCENT TECHNOLOGIES INC

Inventor： VITKAVAGE DANIEL JOSEPH ,  ALERS GLENN B ,  LEE TSENG-CHUNG ,  MAYNARD HELEN LOUISE

IPC: H01L27/10 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/108

Abstract: A capacitor structure situated in window (101, Fig. 1) of dielectric layer (D 2 ) of an integrated circuit comprises lower electrode (102), dielectric layer (405) and upper electrode (406). The lower electrode (102) is disposed on side surface of cavity (101, Fig. 1), but not on the top surface of layer (D 2 ), and the top end of the lower electrode (102) is preferably about 0.2 microns below the top surface of the layer (D 2 ). The lower electrode (102) may be in contact with conductive plug (609), and the dielectric layer (405) is preferably tantalum oxide. A process for fabricating an integrated circuit is also disclosed, where lower capacitor plate (102) is deposited on both the sidewalls of the opening and the top surface of layer (D 2 ), and then the lower plate (102) is etched from the top surface and a portion of the sidewalls.

公开(公告)号：GB2350929B

公开(公告)日：2002-05-22

申请号：GB0009611

申请日：2000-04-18

Applicant: LUCENT TECHNOLOGIES INC

Inventor： VITKAVAGE DANIEL JOSEPH ,  ALERS GLENN B ,  LEE TSENG-CHUNG ,  MAYNARD HELEN LOUISE

IPC: H01L27/10 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/108

Abstract: A capacitor structure is formed in a window in a dielectric layer of an integrated circuit. The lower electrode (or plate) is disposed on a portion side surface of the cavity but not on the top surface of the dielectric. A layer of dielectric material is disposed on the lower electrode and upon the top surface of the integrated circuit dielectric. Finally, an upper electrode (or plate) is disposed on the layer of dielectric material. Because the lower electrode is removed from a portion of the cavity sidewall and top surface of the dielectric shorting problems which could result during planarization are avoided. A technique for fabricating an integrated circuit (IC) for use in multi-level structures is also disclosed. The technique is readily incorporated into standard multi-level processing techniques. After a window is opened in the particular dielectric layer of the IC, a conductive layer is deposited in the window and forms the lower plate of a capacitor. The lower plate is then etched so that it is removed from a portion of the sidewalls and from the top surface of the dielectric layer. After the lower electrode is etched, a dielectric material is disposed in the cavity and on the top surface of the dielectric layer. A second layer of conductor is disposed on top of the dielectric material layer, thus completing the capacitor structure.

公开(公告)号：EP0768512A3

公开(公告)日：1998-10-21

申请号：EP96307479

申请日：1996-10-15

Applicant: LUCENT TECHNOLOGIES INC

Inventor： LEE TSENG-CHUNG ,  MAYNARD HELEN LOUISE

IPC: G01B11/06 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/66

CPC classification number: G01B11/0616

Abstract: A process for device fabrication in which polarized light is used to monitor film thickness. The polarized light is made incident on the surface of a substrate with a film thereon that has a different reflectivity than that of the underlying substrate. The surface of the film is non-planar, either by virtue of the fact that the film is formed over a substrate with a non-planar surface, or because there is a patterned layer formed over the film, or both. The substrate is subjected to conditions that change the thickness of the film on the substrate. The polarized light that is reflected from the substrate is detected at a selected wavelength or wavelengths and a trace of the intensity of the reflected light both parallel and perpendicular to the substrate surface over time is obtained. This trace is compared to a model trace which is obtained by approximating the film thickness, and the relative amount of the areas of different reflectivity on the substrate surface. The film thickness used to generate the model trace is adjusted to obtain a desired correspondence between the model trace and the actual trace. When the desired correspondence is obtained, then the film thickness used to obtain the model trace with the desired correspondence is the determined film thickness.