公开(公告)号：GB2364598A

公开(公告)日：2002-01-30

申请号：GB0100169

申请日：2001-01-04

Applicant: LUCENT TECHNOLOGIES INC

Inventor： CWYNAR DONALD THOMAS ,  MISRA SUDHANSHU ,  OUMA DENNIS OKUMU ,  SAXENA VIVEK ,  SHARPE JOHN MICHAEL

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/82 ,  H01L23/528 ,  H01L27/04 ,  H01L21/02

Abstract: A method for making a layout for an interconnect layer of a semiconductor device to facilitate uniformity of planarization during manufacture of the semiconductor device includes determining an active interconnect feature density for each of a plurality of layout regions 60(1)-60(n) of the interconnect layout (30, Figure 5). The method further includes adding dummy fill features 74(1)-74(n) to the layout region to obtain a desired density of active interconnect features 70(1)-70(n) and dummy fill features 74(1)-74(n) to facilitate uniformity of planarization during the manufacturing of the semiconductor device. The positions of the dummy film features 74(1)-74(n) may be based upon capacitance with adjacent active interconnect features, or with capacitance with adjacent active interconnect features in an adjacent interconnect layer. The dummy fill features 74(1)-74(n) may have a minimum dummy fill feature lateral dimension based upon a dielectric layer deposition bias for a dielectric layer deposited over the interconnect layer. A semiconductor device has a substrate and at least one interconnect layer overlying the semiconductor substrate comprising a plurality of layout regions. Each layout region 60(1)-60(n) comprises an active interconnect feature region and a dummy fill feature region adjacent thereto for facilitating uniformity of planarization during manufacture the semiconductor device. Each of the dummy fill regions has a different density with respect to other dummy fill regions so that a combined density of the active interconnect feature region and the dummy fill feature region for a respective layout region is substantially uniform with respect to the combined density of other layer regions. The density of the active interconnect features for a respective layout region may be determined using a layout algorithm.