公开(公告)号：JP2001237331A

公开(公告)日：2001-08-31

申请号：JP2001011598

申请日：2001-01-19

Applicant: LUCENT TECHNOLOGIES INC

Inventor： SINGH RANBIR ,  II FEN CHAN ,  CHAN WEI REN

IPC: H01L21/331 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8247 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L27/092 ,  H01L27/115 ,  H01L29/73 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a flash memory device which can operate in a short read time. SOLUTION: The bipolar transistor used to increase the operational speed of a flash memory cell having source and drain regions and first and second complementary tubs, includes a base formed in the first complementary tub and functioning as the source region and an emitter formed in the first complementary tub adjacent to the base. The first complementary tub functions as a collector of the bipolar transistor.

公开(公告)号：JP2001185632A

公开(公告)日：2001-07-06

申请号：JP2000378314

申请日：2000-12-13

Applicant: LUCENT TECHNOLOGIES INC

Inventor： SINGH RANBIR ,  PATRICK J KELLY ,  LEUNG CHUNG WAI

IPC: G11C16/02 ,  G11C16/04 ,  G11C16/14 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide an EEPROM in which the reliability and the data retaining capability do not deteriorate. SOLUTION: The electrically erasable memory device comprises a plurality of memory cells, each memory cell comprising a first N type region in a substrate, a first MOS transistor comprising spaced apart source and drain regions and a gate, a second P type region in the substrate laterally adjacent to the first region, a capacitor comprising a first electrode formed on the second region through an insulation layer and a third N type region (second electrode), the gate of the first MOS transistor and the first electrode being connected to define a floating gate and the second region serving as a control gate, and an erasing circuit for selectively erasing at least one of the memory cells by supplying a first positive voltage reference to the source and drain regions of the first MOS transistor and a third negative voltage reference to the third region.

公开(公告)号：JP2001196468A

公开(公告)日：2001-07-19

申请号：JP2000366458

申请日：2000-12-01

Applicant: LUCENT TECHNOLOGIES INC

Inventor： KIZILYALLI ISIK C ,  SINGH RANBIR ,  LORI STERLING

IPC: H01L27/092 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/105 ,  H01L29/49

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device that reduces no density of channel carries and the switching rate of a device and causes no time delay, or no malfunction of a gate. SOLUTION: In a semiconductor device 100 provided on a semiconductor substrate where first and second transistors 115 and 120 of completely opposite types are formed, the semiconductor device includes a first gate electrode 155 containing a first metal gate electrode material with a work function compatible with the first transistor 115, and a second gate electrode 160 containing a second metal gate electrode material with a work function compatible with the second transistor 120. Also, in the second gate electrode 160, a first metal gate electrode material 162b is also provided on a second metal gate electrode material 162a, thus forming a gate stack.

公开(公告)号：GB2364438A

公开(公告)日：2002-01-23

申请号：GB0100173

申请日：2001-01-04

Applicant: LUCENT TECHNOLOGIES INC

Inventor： CHYAN YIH-FENG ,  LEUNG CHUNG WAI ,  SINGH RANBIR

IPC: H01L21/331 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8247 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L27/092 ,  H01L27/115 ,  H01L29/73 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8248

Abstract: The present invention provides a bipolar transistor 620 for use in increasing a speed of a flash memory cell 610 having a source region and a drain region and first and second complementary tubs 115,(120). A base 210 for the bipolar transistor is located in the first complementary tub 115. The first complementary tub functions as a collector for the bipolar transistor. The bipolar transistor base 210 uniquely functions as the source or drain region. The bipolar transistor's emitter 510 is also located in the first complementary tub and proximate the base. For example, the emitter may be actually located in the base (as in fig 6). In an alternative embodiment, the base and emitter are located on opposite sides of the gate. The flash memory cell maybe integrated with CMOS devices 630.

公开(公告)号：GB2364438B

公开(公告)日：2003-01-15

申请号：GB0100173

申请日：2001-01-04

Applicant: LUCENT TECHNOLOGIES INC

Inventor： CHYAN YIH-FENG ,  LEUNG CHUNG WAI ,  SINGH RANBIR

IPC: H01L21/331 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8247 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L27/092 ,  H01L27/115 ,  H01L29/73 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8248

Abstract: The present invention provides a bipolar transistor for use in increasing a speed of a flash memory cell having a source region and a drain region and first and second complementary tubs. In one embodiment, a base for the bipolar transistor is located in the first complementary tub. The first complementary tub functions as a collector for the bipolar transistor. The bipolar transistor base also uniquely functions as the source region. The bipolar transistor's emitter is also located in the first complementary tub and proximate the base. For example, the emitter may be located adjacent the base or actually located in the base. In an additional embodiment, the opposing bases and emitters are located on opposing sides of and proximate to the flash memory cell.

公开(公告)号：GB2363903A

公开(公告)日：2002-01-09

申请号：GB0028873

申请日：2000-11-27

Applicant: LUCENT TECHNOLOGIES INC

Inventor： KIZILYALLI ISIK C ,  SINGH RANBIR ,  STIRLING LORI

IPC: H01L27/092 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/105 ,  H01L29/49

Abstract: A method of manufacturing a semiconductor device 100 comprises, forming a first gate electrode 155, a first metal gate electrode material having a work function compatible with a first transistor 115, and forming a second gate electrode 160 of a second metal gate electrode material having a work function compatible with a second transistor 120. The first and second transistors 115, 120 are of opposite types and are formed on a semiconductor substrate. In a semiconductor device 100 the first metal gate electrode material 162b is located over the second metal gate electrode material 162a. The first gate electrode may be formed from a material having a work function of about 4.2 eV and the second gate electrode may be formed from a material having a work fuction of 5.2 eV. The first electrode gate material may be tantalum, tungsten, titanium, or titanium nitride, and the second electrode gate material may be tungsten silicide. The semiconductor device may have at least one n+ doped polysilicon electrode (Figures 7, 8 and 9). There may be a metal etch barrier layer having a high dielectric constant formed from tantalum pentoxide, silicon nitride or aluminium oxide. An integrated circuit includes the semiconductor device and has interconnnects electrically connecting the transistors.

公开(公告)号：GB2363679A

公开(公告)日：2002-01-02

申请号：GB0030011

申请日：2000-12-08

Applicant: LUCENT TECHNOLOGIES INC

Inventor： KELLEY PATRICK J ,  LEUNG CHUNG WAI ,  SINGH RANBIR

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/02 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: An electrically erasable memory device (10) such as an EEPROM includes a substrate (12) and a plurality of single poly layer memory cells (14) in the substrate. Each single poly layer memory cell (14) includes a MOS transistor (18) in a first region (16) in the substrate and spaced apart source and drain regions (20, 22). Each single poly layer memory cell further includes a capacitor (32) having a first electrode (34) overlying a second region (30) in the substrate and an insulating layer (36) therebetween, and a third region (38) in the second region defining a second electrode. The first electrode (34) is coupled to the gate (26) of the transistor (18) to form a floating gate (40). An erasing circuit (42) selectively erases the single poly layer memory cell by supplying a first voltage reference of a first polarity to the spaced apart source and drain regions, a second voltage reference of a second polarity to the first region, and a third voltage reference of the second polarity to the second electrode of the capacitor. The first and second voltage references bias the MOS transistor so that the third voltage reference for erasing the single poly layer memory cell does not cause a junction breakdown of the MOS transistor.