公开(公告)号：JP2001358065A

公开(公告)日：2001-12-26

申请号：JP2001111006

申请日：2001-04-10

Applicant: LUCENT TECHNOLOGIES INC

Inventor： DAVID MAKUERUROI BOURIN ,  FARROW REGINALD CONWAY ,  KIZILYALLI ISIK C ,  NEISU RAYADI ,  MKRTCHYAN MASIS

IPC: G03F7/20 ,  G03F9/00 ,  H01J37/304 ,  H01J37/305 ,  H01L21/027 ,  H01L23/544

Abstract: PROBLEM TO BE SOLVED: To provide a method capable of using by forming an alignment feature in a multilayer semiconductor structure or on the multilayer semiconductor structure and connecting the feature to an SCALPEL tool. SOLUTION: A method for forming a multilayer semiconductor structure has the alignment feature to match a lithography mask and capable of using together with the SCALPEL tool. The method is particularly suitable for submicron CMOS technical device and circuit, but not limited only to them. The method is advantageous since the method can use an electron beam source in both matching and exposing the lithography mask on a semiconductor wafer. The method is advantageous since the alignment feature can be formed at an early stage (that is, a zero level) in a step of manufacturing a semiconductor device.

公开(公告)号：JPH10308353A

公开(公告)日：1998-11-17

申请号：JP10638098

申请日：1998-04-16

Applicant: LUCENT TECHNOLOGIES INC

Inventor： KIZILYALLI ISIK C

IPC: H01L21/205 ,  H01L21/336 ,  H01L29/786 ,  H01L31/04

Abstract: PROBLEM TO BE SOLVED: To inhibit deterioration of the efficiency own aging for a device by a method wherein an equivalent concentration of hydrogen isotope is used for passivating an amorphous silicon film. SOLUTION: Unsaturated silicon/dangling bond sites 14 in a substrate 12 with at least one part consisting of an amorphous silicon film are subjected to a passivation treatment with an equivalent concentration of hydrogen isotope (heavy hydrogen). The hydrogen isotope concentrates in one part of the plane- shaped surface of the substrate and when the hydrogen isotope is made to couple with the material for the substrate, it becomes difficult to remove the hydrogen isotope from the coupling because the mass of the hydrogen isotope is larger than that of normal hydrogen and the coupling is made hard to break. Thereby, higher-reliability optical and electrical devices can be formed. Moreover, as this material shows a microscopic structure, the stability of the devices can be also improved.

公开(公告)号：JP2001036068A

公开(公告)日：2001-02-09

申请号：JP2000189020

申请日：2000-06-23

Applicant: LUCENT TECHNOLOGIES INC

Inventor： KIZILYALLI ISIK C ,  MASTRAPASQUA MARCO

IPC: H01L29/68

Abstract: PROBLEM TO BE SOLVED: To improve the performance of an RST device and at the same time easily incorporate the device into a silicon MOS sequence by setting a charge- injection transistor where the conductive band energy level of a first barrier layer is larger than the conductive band of a second barrier layer at least by a specific value. SOLUTION: A first barrier layer 302 is formed on a substrate 301, a second barrier layer 303 made of oxide is formed on the first barrier layer 302, and a layer 304 is formed on the second barrier layer 303. Then, a hot carrier jumps over the first barrier layer 302 and is implanted into the layer 304 that is formed on the second barrier layer 303. Then, the first barrier layer 302 is thinner as it causes the tunnel phenomenon of the hot carrier, and the second barrier layer 303 is thicker than the first barrier layer 302 and reduces a leak current. Then, a dielectric material with a high permittivity is used as the second barrier layer 303, and a silicon dioxide layer that has a thickness of 20 Å or less and has grown is used as the first barrier layer 302.

公开(公告)号：JPH1174265A

公开(公告)日：1999-03-16

申请号：JP16977498

申请日：1998-06-17

Applicant: LUCENT TECHNOLOGIES INC

Inventor： BRADY DAVID C ,  KIZILYALLI ISIK C ,  ROY PRADIP K ,  VAIDYA HEM M

IPC: H01L21/316 ,  H01L21/318 ,  H01L21/32 ,  H01L21/76

Abstract: PROBLEM TO BE SOLVED: To prevent lifting phenomenon of a laminate of a semiconductor structure, especially with a pad oxide layer by constituting an insulative structured body of a uniform thickness by forming a first laminated sub-layer at a first deposit speed and a second laminated sub-layer at a second deposit speed on a substrate one by one. SOLUTION: A first laminated sub-layer is formed at a first deposit speed and a second laminated sub-layer is formed at a second deposit speed on a substrate, constituting an insulation structure body of a uniform thickness. The first deposit speed in the range of 0.5 to 1 nm/minute is desirable, and the second deposit velocity in the range of 3 to 5 nm/minute is desirable. Move specifically, a field oxide 20 is insulated and formed between insulation structure bodies 16 on a semiconductor wafer 10. The thin field oxide 20 of about 150 to 250 nm reduces a length of bird's beak and reduces relief phenomenon of a lamination body. A stress inside the insulation structure body 16 is reduced since the lifting phenomenon is reduced.

公开(公告)号：JP2000232165A

公开(公告)日：2000-08-22

申请号：JP2000029859

申请日：2000-02-08

Applicant: LUCENT TECHNOLOGIES INC

Inventor： COCHRAN WILLIAM THOMAS ,  KIZILYALLI ISIK C ,  THOMA MORGAN JONES

IPC: H01L21/28 ,  H01L21/77 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49

Abstract: PROBLEM TO BE SOLVED: To provide a process for manufacturing a joint integrated circuit device on a semiconductor wafer substrate. SOLUTION: In a process for manufacturing joint integrated circuit device, a gate oxide 530, a first transistor having a first gate 540, and a second transistor having a second gate 500 are successively formed on a semiconductor wafer substrate 510. The first transistor is optimized to a first operating voltage by changing the physical characteristics of the first gate 540, a first tab doping profile, or a first source/drain doping profile. The second transistor is optimized to a second operating voltage by changing the physical characteristics of the second gate 550 or the second source/drain doping profile of the second transistor. The operating voltages of the transistors are optimized to prescribed values by combinedly or independently changing the physical characteristics of the gates 540 and 550.

公开(公告)号：JP2000183349A

公开(公告)日：2000-06-30

申请号：JP35361499

申请日：1999-12-13

Applicant: LUCENT TECHNOLOGIES INC

Inventor： KIZILYALLI ISIK C ,  MERCHANT SAILESH MANSINH ,  ROY PRADIP K

IPC: H01L29/78 ,  C23C14/06 ,  H01L21/28 ,  H01L21/283 ,  H01L21/285 ,  H01L21/336 ,  H01L29/49 ,  H01L29/51

Abstract: PROBLEM TO BE SOLVED: To improve the material of a gate electrode by composing a composite gate electrode of a tungsten silicide nitride layer as an oxygen diffusion barrier layer and of a tungsten silicide layer deposited on the tungsten silicide nitride layer. SOLUTION: A field oxide region 12 and a gate dielectric layer 13 made of tantalum pentoxide are formed on a silicon substrate 11 by a MOSVD method, and another silicon dioxide layer is formed. Then, a tungsten silicide nitride layer 17 is deposited on the layer 13 as an oxygen diffusion barrier layer, and a tungsten silicide layer 18 is deposited on the layer 17, thereby forming a composite gate electrode 16. A source region 21 and a drain region 22 are formed by ion implantation with the electrode 16 as a mask. As a result, the material of the electrode 16 can be improved.

公开(公告)号：JPH11260938A

公开(公告)日：1999-09-24

申请号：JP1568499

申请日：1999-01-25

Applicant: LUCENT TECHNOLOGIES INC

Inventor： GREGOR RICHARD WILLIAM ,  KIZILYALLI ISIK C ,  ROY PRADIP K

IPC: H01L21/8247 ,  H01L21/28 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To produce a floating gate structure having a gate made of polysilicon and dielectric characteristics suitable particularly for a flash memory device, by changing dielectric material composing a gate structure and by setting the thickness of layer of a laminated structure in a predetermined range in manufacturing the floating gate structure. SOLUTION: A gate structure has a second dielectric layer 34 between a floating gate 32 made of polysilicon and a control gate 33 made of polysilicon. The second dielectric layer 34 has a laminated structure comprising a first SiO2 layer 35 having a thickness of 10 to 35 Å, a Ta2 O5 layer having a thickness of 30 to 100 Å, and a second SiO2 layer 37 having a thickness of 5 to 30 Å, and the thickness of second dielectric layer 34 is set in a range of 45 to 150 Å. This can produce a floating gate structure having a gate made of polysilicon and dielectric characteristics suitable for a flush memory device.

公开(公告)号：JPH11195750A

公开(公告)日：1999-07-21

申请号：JP36648197

申请日：1997-12-24

Applicant: LUCENT TECHNOLOGIES INC

Inventor： KIZILYALLI ISIK C ,  MA YI ,  ROY PRADIP K

IPC: H01L27/04 ,  H01L21/822

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing an integrated circuit device which is capable of using a high dielectric material having a high relative permittivity, by reducing defects and leakages thereof. SOLUTION: A method for manufacturing an integrated circuit having an oxidizable layer 2 with a surface has a step A of growing an oxide layer 3 on the surface of the oxidizable layer. The step A includes a step B of depositing a high k dielectric layer 4 on the grown oxide layer, and a step C of depositing an oxide layer 5 on the high k dielectric layer 4. The integrated circuit, which has the oxidizable layer 2 having the oxide layer 3 grown thereon, has the high k dielectric layer 4 on the grown oxide layer 3 and the oxide layer 5 deposited on the high k dielectric layer 4.

公开(公告)号：JP2001044140A

公开(公告)日：2001-02-16

申请号：JP2000189026

申请日：2000-06-23

Applicant: LUCENT TECHNOLOGIES INC

Inventor： KIZILYALLI ISIK C ,  MA YI ,  MERCHANT SAILESH MANSINH ,  PRADIP KUMAR ROY

IPC: H01L21/283 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a gate dielectric structure which can increase the level of integration of an integrated circuit and can miniaturize the circuit by reducing the characteristic size of the circuit to avoid the problem which arises in an extremely thin silicon oxide film in the conventional structure, and a method for manufacturing the structure. SOLUTION: An integrated circuit has a gate stack structure, having a dielectric material layer 103 formed between a substrate 101 and a gate electrode 104. The layer 103 has a

公开(公告)号：JP2000232208A

公开(公告)日：2000-08-22

申请号：JP35361599

申请日：1999-12-13

Applicant: LUCENT TECHNOLOGIES INC

Inventor： KIZILYALLI ISIK C ,  MERCHANT SAILESH MANSINH ,  ROY PRADIP K ,  WONG YIU-HUEN

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/285 ,  H01L21/82 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To add a buried memory to a capacitor without making a sharp change to the manufacturing process of the capacitor by a method wherein in the case where the dielectric layer of the capacitor is formed of a tantalum pentaoxide (Ta2O5) layer, a diffused barrier layer formed of a tungsten nitride(WN) layer instead of a titanium nitride(TiN) layer is provided in the capacitor. SOLUTION: A transistor structure 205 and an interconnected part 210 coming into contact with a capacitor 215 are shown as parts of a buried memory cell structure 200. The capacitor 215 has a first (bottom) electrode comprising a conductive layer 220 for adhesion, a barrier layer 225, which is formed on the interconnected part 210 and consists of a tungsten nitride layer or a tungsten silicon nitride layer, and a dielectric layer 230 and a titanium layer on the first electrode, a second electrode 240 on the layer 230 and a layer 235, which is used as a selective matter, reduce the layer 230. A first layer on the interconnected region is made of the titanium layer and the material for the layer 225 is the tungsten nitride(WN) layer, the tungsten silicon nitride(WSiN) layer or a combination of the tungsten nitride(WN) layer to the tungsten silicon nitride(WSiN) layer.