公开(公告)号：JP2000286336A

公开(公告)日：2000-10-13

申请号：JP2000004807

申请日：2000-01-13

Applicant: LUCENT TECHNOLOGIES INC

Inventor： LYTLE STEVEN ALAN ,  WOLF THOMAS MICHAEL ,  YEN ALLEN

IPC: H01L23/522 ,  H01L21/28 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To form an integrated circuit of a stacked structure having a large cross-sectional shape by forming a through hole or a contact of a through conductor under a hard mask and a second photoresist layer, using both the hard mask and the second photoresist layer as a mask. SOLUTION: In a dielectric layer 1, two conductors 3, 5 are formed. A silicon nitride hard mask 7 is formed above these conductors 3, 5 and a first photoresist layer is formed on the hard mask 7. Then, the first photoresist layer is removed and a second photoresist layer 15 is formed. The second photoresist layer 15 is patterned to form second slender openings 17, 19 stretching across a trench 13. Then, third square openings 18, 20 are formed from the bottom of the trench 13 up to the top of the conductors 3, 5. By a metallization process for filling the openings 18, 20 and a following flattening process for the second photoresist layer 15 and the hard mask 7, a desired square contact like the through conductors is formed.

公开(公告)号：GB2356739B

公开(公告)日：2002-04-17

申请号：GB0019481

申请日：2000-08-08

Applicant: LUCENT TECHNOLOGIES INC

Inventor： MA YI ,  YEN ALLEN

IPC: H01L29/78 ,  H01L21/20 ,  H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L29/10 ,  H01L29/423

Abstract: A method for making a transistor includes the steps of providing a silicon substrate including a silicon-germanium epitaxial layer, forming a masking implant layer on a channel region of the silicon-germanium epitaxial layer, and implanting dopants into the silicon-germanium epitaxial layer using the masking implant layer to define spaced apart source and drain regions adjacent the channel region. The method further includes the step of removing the masking implant layer after the implanting to expose the channel region. A silicon epitaxial layer is formed on the exposed channel region, and at least a portion of the silicon epitaxial layer is converted to silicon oxide to define a gate dielectric layer for the transistor. The gate dielectric layer includes a gate oxide layer, and a silicon protection layer between the gate oxide layer and the channel region. A conductive gate is formed on an upper surface of the gate oxide layer. Since the gate dielectric layer does not include germanium, a stable gate dielectric layer is provided for the high speed silicon-germanium transistor.

公开(公告)号：GB2346009B

公开(公告)日：2002-03-20

申请号：GB0000740

申请日：2000-01-13

Applicant: LUCENT TECHNOLOGIES INC

Inventor： LYTLE STEVEN ALAN ,  WOLF THOMAS MICHAEL ,  YEN ALLEN

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/538

Abstract: The invention includes a process for manufacturing an integrated circuit, comprising providing a substrate comprising a dielectric layer over a conductive material, depositing a hardmask over the dielectric layer, applying a first photoresist over the hardmask and photodefining a trench, etching the hard mask and partially etching the dielectric to form a trench having a bottom, stripping the photoresist, applying a second photoresist and photodefining a slit across the trench, selectively etching the dielectric from the bottom of the trench down to the underlying conductive material. Both the hardmask and the second photoresist are used as a mask. Later, a connection to the underlying metal is formed and integrated circuits made thereby.

公开(公告)号：GB2356739A

公开(公告)日：2001-05-30

申请号：GB0019481

申请日：2000-08-08

Applicant: LUCENT TECHNOLOGIES INC

Inventor： MA YI ,  YEN ALLEN

IPC: H01L29/78 ,  H01L21/20 ,  H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L29/10 ,  H01L29/423

Abstract: A method for making a transistor includes the steps of providing a silicon substrate including a silicon-germanium epitaxial layer, forming a masking implant layer on a channel region of the silicon-germanium epitaxial layer, and implanting dopants into the silicon-germanium epitaxial layer using the masking implant layer to define spaced apart source and drain regions adjacent the channel region. The method further includes the step of removing the masking implant layer after the implanting to expose the channel region. A silicon epitaxial layer is formed on the exposed channel region, and at least a portion of the silicon epitaxial layer is converted to silicon oxide to define a gate dielectric layer for the transistor. The gate dielectric layer includes a gate oxide layer, and a silicon protection layer between the gate oxide layer and the channel region. A conductive gate is formed on an upper surface of the gate oxide layer. Since the gate dielectric layer does not include germanium, a stable gate dielectric layer is provided for the high speed silicon-germanium transistor.

公开(公告)号：GB2346009A

公开(公告)日：2000-07-26

申请号：GB0000740

申请日：2000-01-13

Applicant: LUCENT TECHNOLOGIES INC

Inventor： LYTLE STEVEN ALAN ,  WOLF THOMAS MICHAEL ,  YEN ALLEN

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/538

Abstract: The invention includes a process for manufacturing an integrated circuit, comprising providing a substrate comprising a dielectric layer 1 over a conductive material, 3, 5 depositing a hardmask 7 over the dielectric layer 1 applying a first photoresist 9 over the hardmask 7 and photodefining at least one elongated opening 11 etching the hard mask and partially etching the dielectric 1 to form a trench 13 having a bottom, stripping the photoresist, 9 applying a second photoresist 15 and photodefining a slit 14, 19 across the trench, 13 selectively etching the dielectric from the bottom of the trench down to the underlying conductive material. Both the hardmask and the second photoresist are used as a mask. Preferably a connection to the conductive materials 3, 5 is formed and integrated circuits made thereby. Preferably, one of the connections has a quadrilateral cross-section of less than 0.5 micron.